^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Orion SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Shadi Ammouri <shadi@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2008 Marvell Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRIVER_NAME "orion_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPI_AUTOSUSPEND_TIMEOUT 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Some SoCs using this driver support up to 8 chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * It is up to the implementer to only use the chip selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * that are available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ORION_NUM_CHIPSELECTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ORION_SPI_IF_CTRL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ORION_SPI_IF_CONFIG_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ORION_SPI_IF_RXLSBF BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ORION_SPI_IF_TXLSBF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ORION_SPI_DATA_OUT_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ORION_SPI_DATA_IN_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ORION_SPI_INT_CAUSE_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ORION_SPI_TIMING_PARAMS_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Register for the "Direct Mode" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ORION_SPI_MODE_CPOL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ORION_SPI_MODE_CPHA (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ORION_SPI_MODE_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ORION_SPI_CS_MASK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ORION_SPI_CS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ORION_SPI_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum orion_spi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ORION_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ARMADA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct orion_spi_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum orion_spi_type typ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * min_divisor and max_hz should be exclusive, the only we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * have both is for managing the armada-370-spi case with old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long max_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int min_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int max_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 prescale_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool is_errata_50mhz_ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct orion_direct_acc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct orion_child_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct orion_direct_acc direct_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct orion_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk *axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct orion_spi_dev *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct orion_child_options child[ORION_NUM_CHIPSELECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return orion_spi->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *reg_addr = spi_reg(orion_spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = readl(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *reg_addr = spi_reg(orion_spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = readl(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 tclk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct orion_spi_dev *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) devdata = orion_spi->devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tclk_hz = clk_get_rate(orion_spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (devdata->typ == ARMADA_SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Given the core_clk (tclk_hz) and the target rate (speed) we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * determine the best values for SPR (in [0 .. 15]) and SPPR (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * [0..7]) such that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * core_clk / (SPR * 2 ** SPPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * is as big as possible but not bigger than speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* best integer divider: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned spr, sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (divider < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* This is the easy case, divider is less than 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spr = divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sppr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned two_pow_sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Find the highest bit set in divider. This and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * three next bits define SPR (apart from rounding).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * SPPR is then the number of zero bits that must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * appended:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sppr = fls(divider) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * As SPR only has 4 bits, we have to round divider up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * to the next multiple of 2 ** sppr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) two_pow_sppr = 1 << sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * recalculate sppr as rounding up divider might have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * increased it enough to change the position of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * highest set bit. In this case the bit that now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * doesn't make it into SPR is 0, so there is no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * round again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sppr = fls(divider) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spr = divider >> sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Now do range checking. SPR is constructed to have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * width of 4 bits, so this is fine for sure. So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * still need to check for sppr to fit into 3 bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (sppr > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * the supported rates are: 4,6,8...30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * round up as we look for equal or less speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rate = DIV_ROUND_UP(tclk_hz, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rate = roundup(rate, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* check if requested speed is too small */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (rate > 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (rate < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rate = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Convert the rate to SPI clock divisor value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) prescale = 0x10 + rate/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg = ((reg & ~devdata->prescale_mask) | prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) orion_spi_mode_set(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reg &= ~ORION_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg |= ORION_SPI_MODE_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg |= ORION_SPI_MODE_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Erratum description: (Erratum NO. FE-9144572) The device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * SPI interface supports frequencies of up to 50 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * However, due to this erratum, when the device core clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 250 MHz and the SPI interfaces is configured for 50MHz SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * clock and CPOL=CPHA=1 there might occur data corruption on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * reads from the SPI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Erratum Workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Work in one of the following configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Register".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Register" before setting the interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (clk_get_rate(orion_spi->clk) == 250000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) speed == 50000000 && spi->mode & SPI_CPOL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg |= ORION_SPI_TMISO_SAMPLE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * called only when no transfer is active on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int speed = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if ((t != NULL) && t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) speed = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if ((t != NULL) && t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) orion_spi_mode_set(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (orion_spi->devdata->is_errata_50mhz_ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) orion_spi_50mhz_ac_timing_erratum(spi, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rc = orion_spi_baudrate_set(spi, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (bits_per_word == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ORION_SPI_IF_8_16_BIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ORION_SPI_IF_8_16_BIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void orion_spi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * If this line is using a GPIO to control chip select, this internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * .set_cs() function will still be called, so we clear any previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * chip select. The CS we activate will not have any elecrical effect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * as it is handled by a GPIO, but that doesn't matter. What we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * is to deassert the old chip select and assert some other chip select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ORION_SPI_CS(spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Chip select logic is inverted from spi_set_cs(). For lines using a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * in the GPIO library, but we don't care about that, because in those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * cases we are dealing with an unused native CS anyways so the polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) orion_spi_write_read_8bit(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const u8 **tx_buf, u8 **rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void __iomem *tx_reg, *rx_reg, *int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* clear the interrupt cause register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(0x0, int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (tx_buf && *tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) writel(*(*tx_buf)++, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(0, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (orion_spi_wait_till_ready(orion_spi) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (rx_buf && *rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *(*rx_buf)++ = readl(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) orion_spi_write_read_16bit(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) const u16 **tx_buf, u16 **rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void __iomem *tx_reg, *rx_reg, *int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* clear the interrupt cause register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(0x0, int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (tx_buf && *tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel(0, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (orion_spi_wait_till_ready(orion_spi) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (rx_buf && *rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct orion_spi *orion_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void __iomem *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) word_len = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) count = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) orion_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Use SPI direct write mode if base address is available. Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * fall back to PIO mode for this transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) vaddr = orion_spi->child[cs].direct_access.vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (vaddr && xfer->tx_buf && word_len == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int cnt = count / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int rem = count % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Send the TX-data to the SPI device via the direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * mapped address window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) iowrite32_rep(vaddr, xfer->tx_buf, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (rem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 *buf = (u32 *)xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) iowrite8_rep(vaddr, &buf[cnt], rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (word_len == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const u8 *tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 *rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spi_delay_exec(&xfer->word_delay, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } while (count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else if (word_len == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) const u16 *tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 *rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spi_delay_exec(&xfer->word_delay, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } while (count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return xfer->len - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int orion_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) status = orion_spi_setup_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) orion_spi_write_read(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int orion_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return orion_spi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int orion_spi_reset(struct orion_spi *orion_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Verify that the CS is deasserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Don't deassert CS between the direct mapped SPI transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct orion_spi_dev orion_spi_dev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .typ = ORION_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .min_divisor = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .max_divisor = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct orion_spi_dev armada_370_spi_dev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .typ = ARMADA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .min_divisor = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .max_divisor = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .max_hz = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct orion_spi_dev armada_xp_spi_dev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .typ = ARMADA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .max_hz = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .max_divisor = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct orion_spi_dev armada_375_spi_dev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .typ = ARMADA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .min_divisor = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .max_divisor = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct orion_spi_dev armada_380_spi_dev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .typ = ARMADA_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .max_hz = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .max_divisor = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .is_errata_50mhz_ac = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct of_device_id orion_spi_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .compatible = "marvell,orion-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .data = &orion_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .compatible = "marvell,armada-370-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .data = &armada_370_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .compatible = "marvell,armada-375-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .data = &armada_375_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .compatible = "marvell,armada-380-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .data = &armada_380_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .compatible = "marvell,armada-390-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .data = &armada_xp_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .compatible = "marvell,armada-xp-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .data = &armada_xp_spi_dev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int orion_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const struct orion_spi_dev *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct orion_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long tclk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) master = spi_alloc_master(&pdev->dev, sizeof(*spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_dbg(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (pdev->id != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 cell_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &cell_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) master->bus_num = cell_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* we support all 4 SPI modes and LSB first option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) master->set_cs = orion_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) master->transfer_one = orion_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) master->num_chipselect = ORION_NUM_CHIPSELECTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) master->setup = orion_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) master->flags = SPI_MASTER_GPIO_SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spi->devdata = devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (IS_ERR(spi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) status = PTR_ERR(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) status = clk_prepare_enable(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* The following clock is only used by some SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) status = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto out_rel_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!IS_ERR(spi->axi_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) clk_prepare_enable(spi->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tclk_hz = clk_get_rate(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * With old device tree, armada-370-spi could be used with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Armada XP, however for this SoC the maximum frequency is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * higher than 200MHz. So, in order to be able to handle both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * SoCs, we can take the minimum of 50MHz and tclk/4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "marvell,armada-370-spi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) master->max_speed_hz = min(devdata->max_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) else if (devdata->min_divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) master->max_speed_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) master->max_speed_hz = devdata->max_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) spi->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (IS_ERR(spi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) status = PTR_ERR(spi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto out_rel_axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) for_each_available_child_of_node(pdev->dev.of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct orion_direct_acc *dir_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Get chip-select number from the "reg" property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) status = of_property_read_u32(np, "reg", &cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "%pOF has no valid 'reg' property (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) np, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * Check if an address is configured for this SPI device. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * not, the MBus mapping via the 'ranges' property in the 'soc'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * node is not configured and this device should not use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * direct mode. In this case, just continue with the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Only map one page for direct access. This is enough for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * simple TX transfer which only writes to the first word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * This needs to get extended for the direct SPI NOR / SPI NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * support, once this gets implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dir_acc = &spi->child[cs].direct_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!dir_acc->vaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out_rel_axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dir_acc->size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) status = orion_spi_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto out_rel_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) status = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto out_rel_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) out_rel_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) out_rel_axi_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) clk_disable_unprepare(spi->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) out_rel_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int orion_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct orion_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) clk_disable_unprepare(spi->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int orion_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct orion_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_disable_unprepare(spi->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clk_disable_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int orion_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct orion_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!IS_ERR(spi->axi_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) clk_prepare_enable(spi->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return clk_prepare_enable(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct dev_pm_ops orion_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) orion_spi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static struct platform_driver orion_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .pm = &orion_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .of_match_table = of_match_ptr(orion_spi_of_match_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .probe = orion_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .remove = orion_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) module_platform_driver(orion_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MODULE_DESCRIPTION("Orion SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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