^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2 McSPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005, 2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Juha Yrj�l� <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/spi-omap2-mcspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP2_MCSPI_MAX_FREQ 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP2_MCSPI_MAX_DIVIDER 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP2_MCSPI_MAX_FIFODEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP2_MCSPI_REVISION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP2_MCSPI_SYSSTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP2_MCSPI_IRQSTATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP2_MCSPI_IRQENABLE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP2_MCSPI_WAKEUPENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP2_MCSPI_SYST 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP2_MCSPI_MODULCTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP2_MCSPI_XFERLEVEL 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* per-channel banks, 0x14 bytes each, first is: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP2_MCSPI_CHCONF0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP2_MCSPI_CHSTAT0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP2_MCSPI_CHCTRL0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP2_MCSPI_TX0 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP2_MCSPI_RX0 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* per-register bitmasks: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP2_MCSPI_CHCONF_POL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP2_MCSPI_CHCONF_IS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* We have 2 DMA channels per CS, one for RX and one for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct omap2_mcspi_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct completion dma_tx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct completion dma_rx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) char dma_rx_ch_name[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) char dma_tx_ch_name[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * cache operations; better heuristics consider wordsize and bitrate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DMA_MIN_BYTES 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Used for context save and restore, structure members to be updated whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * corresponding registers are modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct omap2_mcspi_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 modulctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 wakeupenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct list_head cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct omap2_mcspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct completion txdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Virtual base address of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* SPI1 has 4 channels, while SPI2 has 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct omap2_mcspi_dma *dma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct omap2_mcspi_regs ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool slave_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int pin_dir:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) size_t max_xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct omap2_mcspi_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Context save and restore shadow register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 chconf0, chctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void mcspi_write_reg(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int idx, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel_relaxed(val, mcspi->base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return readl_relaxed(mcspi->base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline void mcspi_write_cs_reg(const struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int idx, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel_relaxed(val, cs->base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return readl_relaxed(cs->base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return cs->chconf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cs->chconf0 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline int mcspi_bytes_per_word(int word_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (word_len <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else if (word_len <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else /* word_len <= 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int is_read, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 l, rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) l = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (is_read) /* 1 is read, 0 write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rw = OMAP2_MCSPI_CHCONF_DMAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rw = OMAP2_MCSPI_CHCONF_DMAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) l |= rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) l &= ~rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mcspi_write_chconf0(spi, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) l = cs->chctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) l |= OMAP2_MCSPI_CHCTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) l &= ~OMAP2_MCSPI_CHCTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cs->chctrl0 = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Flash post-writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* The controller handles the inverted chip selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * the inversion from the core spi_set_cs function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enable = !enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (spi->controller_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int err = pm_runtime_get_sync(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pm_runtime_put_noidle(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(mcspi->dev, "failed to get sync: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) l = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) l &= ~OMAP2_MCSPI_CHCONF_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) l |= OMAP2_MCSPI_CHCONF_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mcspi_write_chconf0(spi, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm_runtime_mark_last_busy(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pm_runtime_put_autosuspend(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void omap2_mcspi_set_mode(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct omap2_mcspi_regs *ctx = &mcspi->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Choose master or slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (spi_controller_is_slave(master)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) l |= (OMAP2_MCSPI_MODULCTRL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ctx->modulctrl = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void omap2_mcspi_set_fifo(const struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct spi_transfer *t, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct spi_master *master = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int wcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int max_fifo_depth, bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 chconf, xferlevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) chconf = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bytes_per_word = mcspi_bytes_per_word(cs->word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (t->len % bytes_per_word != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto disable_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (t->rx_buf != NULL && t->tx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) wcnt = t->len / bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto disable_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) xferlevel = wcnt << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (t->rx_buf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) chconf |= OMAP2_MCSPI_CHCONF_FFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) xferlevel |= (bytes_per_word - 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (t->tx_buf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) chconf |= OMAP2_MCSPI_CHCONF_FFET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) xferlevel |= bytes_per_word - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mcspi_write_chconf0(spi, chconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mcspi->fifo_depth = max_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) disable_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (t->rx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (t->tx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mcspi_write_chconf0(spi, chconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mcspi->fifo_depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) while (!(readl_relaxed(reg) & bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!(readl_relaxed(reg) & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct completion *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (spi_controller_is_slave(mcspi->master)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (wait_for_completion_interruptible(x) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mcspi->slave_aborted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) wait_for_completion(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void omap2_mcspi_rx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct spi_device *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* We must disable the DMA RX request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) omap2_mcspi_set_dma_req(spi, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) complete(&mcspi_dma->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void omap2_mcspi_tx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct spi_device *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* We must disable the DMA TX request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) omap2_mcspi_set_dma_req(spi, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) complete(&mcspi_dma->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void omap2_mcspi_tx_dma(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct spi_transfer *xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct dma_slave_config cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct omap2_mcspi_dma *mcspi_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mcspi_dma = &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) xfer->tx_sg.nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tx->callback = omap2_mcspi_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tx->callback_param = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* FIXME: fall back to PIO? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dma_async_issue_pending(mcspi_dma->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) omap2_mcspi_set_dma_req(spi, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct dma_slave_config cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned es)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct omap2_mcspi_dma *mcspi_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int count, transfer_reduction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct scatterlist *sg_out[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int nb_sizes = 0, out_mapped_nents[2], ret, x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) size_t sizes[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int elements = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int word_len, element_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mcspi_dma = &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) count = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * it mentions reducing DMA transfer length by one element in master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * normal mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (mcspi->fifo_depth == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) transfer_reduction = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) word_len = cs->word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) l = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (word_len <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) element_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else if (word_len <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) element_count = count >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else /* word_len <= 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) element_count = count >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Reduce DMA transfer length by one more if McSPI is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * configured in turbo mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) transfer_reduction += es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (transfer_reduction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Split sgl into two. The second sgl won't be used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sizes[0] = count - transfer_reduction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sizes[1] = transfer_reduction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) nb_sizes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Don't bother splitting the sgl. This essentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * clones the original sgl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sizes[0] = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) nb_sizes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sizes, sg_out, out_mapped_nents, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(&spi->dev, "sg_split failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) out_mapped_nents[0], DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tx->callback = omap2_mcspi_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tx->callback_param = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* FIXME: fall back to PIO? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma_async_issue_pending(mcspi_dma->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) omap2_mcspi_set_dma_req(spi, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret || mcspi->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dmaengine_terminate_sync(mcspi_dma->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) omap2_mcspi_set_dma_req(spi, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for (x = 0; x < nb_sizes; x++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) kfree(sg_out[x]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (mcspi->fifo_depth > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Due to the DMA transfer length reduction the missing bytes must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * be read manually to receive all of the expected data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) elements = element_count - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (l & OMAP2_MCSPI_CHCONF_TURBO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) elements--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) OMAP2_MCSPI_CHSTAT_RXS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (word_len <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ((u8 *)xfer->rx_buf)[elements++] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) else if (word_len <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ((u16 *)xfer->rx_buf)[elements++] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else /* word_len <= 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ((u32 *)xfer->rx_buf)[elements++] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int bytes_per_word = mcspi_bytes_per_word(word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_err(&spi->dev, "DMA RX penultimate word empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) count -= (bytes_per_word << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) omap2_mcspi_set_enable(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (word_len <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ((u8 *)xfer->rx_buf)[elements] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else if (word_len <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ((u16 *)xfer->rx_buf)[elements] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else /* word_len <= 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ((u32 *)xfer->rx_buf)[elements] = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(&spi->dev, "DMA RX last word empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) count -= mcspi_bytes_per_word(word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) omap2_mcspi_set_enable(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct omap2_mcspi_dma *mcspi_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const u8 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) enum dma_slave_buswidth width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void __iomem *chstat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) void __iomem *irqstat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int wait_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mcspi_dma = &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (cs->word_len <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) es = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else if (cs->word_len <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) es = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) es = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) count = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) cfg.src_addr_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cfg.dst_addr_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cfg.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) cfg.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mcspi->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reinit_completion(&mcspi_dma->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) reinit_completion(&mcspi_dma->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) reinit_completion(&mcspi->txdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Enable EOW IRQ to know end of tx in slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (spi_controller_is_slave(spi->master))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mcspi_write_reg(spi->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) OMAP2_MCSPI_IRQENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) OMAP2_MCSPI_IRQSTATUS_EOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) omap2_mcspi_tx_dma(spi, xfer, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (rx != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (tx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret || mcspi->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dmaengine_terminate_sync(mcspi_dma->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) omap2_mcspi_set_dma_req(spi, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (spi_controller_is_slave(mcspi->master)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret || mcspi->slave_aborted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (mcspi->fifo_depth > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (mcspi_wait_for_reg_bit(irqstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&spi->dev, "EOW timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) OMAP2_MCSPI_IRQSTATUS_EOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* for TX_ONLY mode, be sure all words have shifted out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (rx == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (mcspi->fifo_depth > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) wait_res = mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) OMAP2_MCSPI_CHSTAT_TXFFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (wait_res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(&spi->dev, "TXFFE timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) wait_res = mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) OMAP2_MCSPI_CHSTAT_TXS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (wait_res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (wait_res >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) OMAP2_MCSPI_CHSTAT_EOT) < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(&spi->dev, "EOT timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int count, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void __iomem *base = cs->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void __iomem *tx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) void __iomem *rx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void __iomem *chstat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) count = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) c = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) word_len = cs->word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) l = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* We store the pre-calculated register addresses on stack to speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * up the transfer loop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tx_reg = base + OMAP2_MCSPI_TX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) rx_reg = base + OMAP2_MCSPI_RX0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (c < (word_len>>3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (word_len <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u8 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) const u8 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) c -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (tx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) OMAP2_MCSPI_CHSTAT_TXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_vdbg(&spi->dev, "write-%d %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) word_len, *tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) writel_relaxed(*tx++, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (rx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(&spi->dev, "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (c == 1 && tx == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (l & OMAP2_MCSPI_CHCONF_TURBO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_vdbg(&spi->dev, "read-%d %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else if (c == 0 && tx == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_vdbg(&spi->dev, "read-%d %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } while (c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else if (word_len <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u16 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) const u16 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) c -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (tx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) OMAP2_MCSPI_CHSTAT_TXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_vdbg(&spi->dev, "write-%d %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) word_len, *tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) writel_relaxed(*tx++, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(&spi->dev, "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (c == 2 && tx == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) (l & OMAP2_MCSPI_CHCONF_TURBO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_vdbg(&spi->dev, "read-%d %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } else if (c == 0 && tx == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_vdbg(&spi->dev, "read-%d %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } while (c >= 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else if (word_len <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) const u32 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) c -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (tx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) OMAP2_MCSPI_CHSTAT_TXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_vdbg(&spi->dev, "write-%d %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) word_len, *tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) writel_relaxed(*tx++, tx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (rx != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(&spi->dev, "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (c == 4 && tx == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (l & OMAP2_MCSPI_CHCONF_TURBO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_vdbg(&spi->dev, "read-%d %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) OMAP2_MCSPI_CHSTAT_RXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "RXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } else if (c == 0 && tx == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) *rx++ = readl_relaxed(rx_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_vdbg(&spi->dev, "read-%d %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) word_len, *(rx - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) } while (c >= 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* for TX_ONLY mode, be sure all words have shifted out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (xfer->rx_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) OMAP2_MCSPI_CHSTAT_TXS) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_err(&spi->dev, "TXS timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) } else if (mcspi_wait_for_reg_bit(chstat_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) OMAP2_MCSPI_CHSTAT_EOT) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_err(&spi->dev, "EOT timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* disable chan to purge rx datas received in TX_ONLY transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * otherwise these rx datas will affect the direct following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * RX_ONLY transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) omap2_mcspi_set_enable(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return count - c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) for (div = 0; div < 15; div++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* called only when no transfer is active to this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int omap2_mcspi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u8 word_len = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (t != NULL && t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) word_len = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cs->word_len = word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (t && t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) clkd = omap2_mcspi_calc_divisor(speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) clkg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clkd = (div - 1) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) extclk = (div - 1) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clkg = OMAP2_MCSPI_CHCONF_CLKG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) l = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * REVISIT: this controller could support SPI_3WIRE mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) l &= ~OMAP2_MCSPI_CHCONF_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) l &= ~OMAP2_MCSPI_CHCONF_DPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) l |= OMAP2_MCSPI_CHCONF_DPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) l |= OMAP2_MCSPI_CHCONF_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) l |= OMAP2_MCSPI_CHCONF_DPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) l &= ~OMAP2_MCSPI_CHCONF_DPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* wordlength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) l |= (word_len - 1) << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* set chipselect polarity; manage with FORCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!(spi->mode & SPI_CS_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) l &= ~OMAP2_MCSPI_CHCONF_EPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* set clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) l |= clkd << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* set clock granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) l &= ~OMAP2_MCSPI_CHCONF_CLKG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) l |= clkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (clkg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) cs->chctrl0 |= extclk << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* set SPI mode 0..3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) l |= OMAP2_MCSPI_CHCONF_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) l &= ~OMAP2_MCSPI_CHCONF_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) l |= OMAP2_MCSPI_CHCONF_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) l &= ~OMAP2_MCSPI_CHCONF_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mcspi_write_chconf0(spi, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) cs->mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) (spi->mode & SPI_CPHA) ? "trailing" : "leading",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) (spi->mode & SPI_CPOL) ? "inverted" : "normal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Note that we currently allow DMA only if we get a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct omap2_mcspi_dma *mcspi_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mcspi_dma->dma_rx_ch_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (IS_ERR(mcspi_dma->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = PTR_ERR(mcspi_dma->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mcspi_dma->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mcspi_dma->dma_tx_ch_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (IS_ERR(mcspi_dma->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = PTR_ERR(mcspi_dma->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) mcspi_dma->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dma_release_channel(mcspi_dma->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mcspi_dma->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) init_completion(&mcspi_dma->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) init_completion(&mcspi_dma->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) no_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static void omap2_mcspi_release_dma(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct omap2_mcspi_dma *mcspi_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) for (i = 0; i < master->num_chipselect; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mcspi_dma = &mcspi->dma_channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (mcspi_dma->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dma_release_channel(mcspi_dma->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) mcspi_dma->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (mcspi_dma->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dma_release_channel(mcspi_dma->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) mcspi_dma->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static void omap2_mcspi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct omap2_mcspi_cs *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (spi->controller_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Unlink controller state from context save list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) list_del(&cs->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int omap2_mcspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) bool initial_setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct omap2_mcspi_regs *ctx = &mcspi->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct omap2_mcspi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cs = kzalloc(sizeof *cs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cs->base = mcspi->base + spi->chip_select * 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) cs->phys = mcspi->phys + spi->chip_select * 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cs->mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) cs->chconf0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) cs->chctrl0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Link this to context save list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) list_add_tail(&cs->node, &ctx->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) initial_setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = pm_runtime_get_sync(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pm_runtime_put_noidle(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) omap2_mcspi_cleanup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = omap2_mcspi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret && initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) omap2_mcspi_cleanup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pm_runtime_mark_last_busy(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pm_runtime_put_autosuspend(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct omap2_mcspi *mcspi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (!irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Disable IRQ and wakeup slave xfer task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) complete(&mcspi->txdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static int omap2_mcspi_slave_abort(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mcspi->slave_aborted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) complete(&mcspi_dma->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) complete(&mcspi_dma->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) complete(&mcspi->txdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int omap2_mcspi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* We only enable one channel at a time -- the one whose message is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * -- although this controller would gladly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * arbitrate among multiple channels. This corresponds to "single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * channel" master mode. As a side effect, we need to manage the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * chipselect with the FORCE bit ... CS != channel enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct omap2_mcspi_dma *mcspi_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct omap2_mcspi_cs *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct omap2_mcspi_device_config *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int par_override = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u32 chconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) mcspi_dma = mcspi->dma_channels + spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) cd = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * The slave driver could have changed spi->mode in which case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * it will be different from cs->mode (the current hardware setup).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * If so, set par_override (even though its not a parity issue) so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * omap2_mcspi_setup_transfer will be called to configure the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * with the correct mode on the first iteration of the loop below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (spi->mode != cs->mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) par_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (par_override ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) (t->speed_hz != spi->max_speed_hz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) (t->bits_per_word != spi->bits_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) par_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) status = omap2_mcspi_setup_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (t->speed_hz == spi->max_speed_hz &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) t->bits_per_word == spi->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) par_override = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (cd && cd->cs_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) chconf = mcspi->ctx.modulctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) mcspi->ctx.modulctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) chconf = mcspi_cached_chconf0(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (t->tx_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) else if (t->rx_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (cd && cd->turbo_mode && t->tx_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Turbo mode is for more than one word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (t->len > ((cs->word_len + 7) >> 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) chconf |= OMAP2_MCSPI_CHCONF_TURBO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mcspi_write_chconf0(spi, chconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) unsigned count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) master->cur_msg_mapped &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) master->can_dma(master, spi, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) omap2_mcspi_set_fifo(spi, t, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) omap2_mcspi_set_enable(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* RX_ONLY mode needs dummy data in TX reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (t->tx_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) writel_relaxed(0, cs->base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) + OMAP2_MCSPI_TX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) master->cur_msg_mapped &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) master->can_dma(master, spi, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) count = omap2_mcspi_txrx_dma(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) count = omap2_mcspi_txrx_pio(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (count != t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (mcspi->fifo_depth > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) omap2_mcspi_set_fifo(spi, t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Restore defaults if they were overriden */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (par_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) par_override = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) status = omap2_mcspi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (cd && cd->cs_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) chconf = mcspi->ctx.modulctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mcspi->ctx.modulctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) omap2_mcspi_set_enable(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (mcspi->fifo_depth > 0 && t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) omap2_mcspi_set_fifo(spi, t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int omap2_mcspi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct omap2_mcspi_regs *ctx = &mcspi->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct omap2_mcspi_cs *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Only a single channel can have the FORCE bit enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * in its chconf0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * Scan all channels and disable them except the current one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * A FORCE can remain from a last transfer having cs_change enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) list_for_each_entry(cs, &ctx->cs, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (msg->spi->controller_state == cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) writel_relaxed(cs->chconf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) cs->base + OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static bool omap2_mcspi_can_dma(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct omap2_mcspi_dma *mcspi_dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (spi_controller_is_slave(master))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) master->dma_rx = mcspi_dma->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) master->dma_tx = mcspi_dma->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return (xfer->len >= DMA_MIN_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct omap2_mcspi_dma *mcspi_dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) &mcspi->dma_channels[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return mcspi->max_xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return SIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct spi_master *master = mcspi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct omap2_mcspi_regs *ctx = &mcspi->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = pm_runtime_get_sync(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pm_runtime_put_noidle(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) OMAP2_MCSPI_WAKEUPENABLE_WKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) omap2_mcspi_set_mode(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pm_runtime_mark_last_busy(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pm_runtime_put_autosuspend(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * When SPI wake up from off-mode, CS is in activate state. If it was in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * inactive state when driver was suspend, then force it to inactive state at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * wake up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static int omap_mcspi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct omap2_mcspi_regs *ctx = &mcspi->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct omap2_mcspi_cs *cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* McSPI: context restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) list_for_each_entry(cs, &ctx->cs, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * We need to toggle CS state for OMAP take this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * change in account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) writel_relaxed(cs->chconf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) cs->base + OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) writel_relaxed(cs->chconf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) cs->base + OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) writel_relaxed(cs->chconf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) cs->base + OMAP2_MCSPI_CHCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct omap2_mcspi_platform_config omap2_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .regs_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static struct omap2_mcspi_platform_config omap4_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .regs_offset = OMAP4_MCSPI_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static struct omap2_mcspi_platform_config am654_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .regs_offset = OMAP4_MCSPI_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .max_xfer_len = SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const struct of_device_id omap_mcspi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .compatible = "ti,omap2-mcspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .data = &omap2_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .compatible = "ti,omap4-mcspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .data = &omap4_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .compatible = "ti,am654-mcspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .data = &am654_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int omap2_mcspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) const struct omap2_mcspi_platform_config *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct omap2_mcspi *mcspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int status = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 regs_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (of_property_read_bool(node, "spi-slave"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) master->setup = omap2_mcspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) master->prepare_message = omap2_mcspi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) master->can_dma = omap2_mcspi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) master->transfer_one = omap2_mcspi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) master->set_cs = omap2_mcspi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) master->cleanup = omap2_mcspi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) master->slave_abort = omap2_mcspi_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) master->dev.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) mcspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) match = of_match_device(omap_mcspi_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u32 num_cs = 1; /* default number of chipselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) master->num_chipselect = pdata->num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) mcspi->pin_dir = pdata->pin_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) regs_offset = pdata->regs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (pdata->max_xfer_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mcspi->max_xfer_len = pdata->max_xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) master->max_transfer_size = omap2_mcspi_max_xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) mcspi->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (IS_ERR(mcspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) status = PTR_ERR(mcspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) mcspi->phys = r->start + regs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mcspi->base += regs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) mcspi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) INIT_LIST_HEAD(&mcspi->ctx.cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sizeof(struct omap2_mcspi_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (mcspi->dma_channels == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) for (i = 0; i < master->num_chipselect; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) status = omap2_mcspi_request_dma(mcspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &mcspi->dma_channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (status == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) status = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (status == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_err(&pdev->dev, "no irq resource found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) init_completion(&mcspi->txdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) status = devm_request_irq(&pdev->dev, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) omap2_mcspi_irq_handler, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) mcspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dev_err(&pdev->dev, "Cannot request IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) status = omap2_mcspi_controller_setup(mcspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) status = devm_spi_register_controller(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) goto disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) disable_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) omap2_mcspi_release_dma(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int omap2_mcspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) omap2_mcspi_release_dma(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) pm_runtime_dont_use_autosuspend(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pm_runtime_put_sync(mcspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MODULE_ALIAS("platform:omap2_mcspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) error = pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) error = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int __maybe_unused omap2_mcspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) error = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) error = spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const struct dev_pm_ops omap2_mcspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) omap2_mcspi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .runtime_resume = omap_mcspi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static struct platform_driver omap2_mcspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .name = "omap2_mcspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .pm = &omap2_mcspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .of_match_table = omap_mcspi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .probe = omap2_mcspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .remove = omap2_mcspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) module_platform_driver(omap2_mcspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags