^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * MicroWire interface driver for OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ported to 2.6 OMAP uwire interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2006 Nokia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Many updates by Imre Deak <imre.deak@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* FIXME address is now a platform device resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * and irqs should show there too...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UWIRE_BASE_PHYS 0xFFFB3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* uWire Registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UWIRE_IO_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UWIRE_TDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UWIRE_RDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UWIRE_CSR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UWIRE_SR1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UWIRE_SR2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UWIRE_SR3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UWIRE_SR4 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UWIRE_SR5 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* CSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RDRB (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSRB (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define START (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CS_CMD (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SR1 or SR2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define UWIRE_READ_FALLING_EDGE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UWIRE_READ_RISING_EDGE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UWIRE_WRITE_FALLING_EDGE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UWIRE_WRITE_RISING_EDGE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UWIRE_CS_ACTIVE_LOW 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UWIRE_CS_ACTIVE_HIGH 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UWIRE_FREQ_DIV_2 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UWIRE_FREQ_DIV_4 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UWIRE_FREQ_DIV_8 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UWIRE_CHK_READY 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UWIRE_CLK_INVERTED 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct uwire_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct uwire_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned div1_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* REVISIT compile time constant for idx_shift? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Or, put it in a structure which is used throughout the driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * that avoids having to issue two loads for each bit of static data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned int uwire_idx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void __iomem *uwire_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void uwire_write_reg(int idx, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline u16 uwire_read_reg(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return __raw_readw(uwire_base + (idx << uwire_idx_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 w, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int shift, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (flags & UWIRE_CLK_INVERTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val ^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = flags & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (cs & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) shift = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (cs <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = UWIRE_SR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = UWIRE_SR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) w = uwire_read_reg(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) w &= ~(0x3f << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) w |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uwire_write_reg(reg, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long max_jiffies = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) w = uwire_read_reg(UWIRE_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if ((w & mask) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (time_after(jiffies, max_jiffies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) printk(KERN_ERR "%s: timeout. reg=%#06x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "mask=%#06x val=%#06x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __func__, w, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) c++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (might_not_catch && c > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void uwire_set_clk1_div(int div1_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) w = uwire_read_reg(UWIRE_SR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) w &= ~(0x03 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) w |= div1_idx << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uwire_write_reg(UWIRE_SR3, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void uwire_chipselect(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct uwire_state *ust = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int old_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) w = uwire_read_reg(UWIRE_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) old_cs = (w >> 10) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Deselect this CS, or the previous CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) w &= ~CS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uwire_write_reg(UWIRE_CSR, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* activate specfied chipselect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (value == BITBANG_CS_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uwire_set_clk1_div(ust->div1_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* invert clock? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) uwire_write_reg(UWIRE_SR4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uwire_write_reg(UWIRE_SR4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) w = spi->chip_select << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) w |= CS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uwire_write_reg(UWIRE_CSR, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 val, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!t->tx_buf && !t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) w = spi->chip_select << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) w |= CS_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const u8 *buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* NOTE: DMA could be used for TX transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* write one or two bytes at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) while (len >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* tx bit 15 is first sent; we byteswap multibyte words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * (msb-first) on the way out from memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (bits > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= *buf++ << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val <<= 16 - bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_debug("%s: write-%d =%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_name(&spi->dev), bits, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (wait_uwire_csr_flag(CSRB, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto eio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uwire_write_reg(UWIRE_TDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* start write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = START | w | (bits << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) uwire_write_reg(UWIRE_CSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) len -= bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Wait till write actually starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * This is needed with MPU clock 60+ MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * REVISIT: we may not have time to catch it...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (wait_uwire_csr_flag(CSRB, CSRB, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto eio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) status += bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* REVISIT: save this for later to get more i/o overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (wait_uwire_csr_flag(CSRB, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto eio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } else if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 *buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* read one or two bytes at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (bits > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* start read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val = START | w | (bits << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uwire_write_reg(UWIRE_CSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) len -= bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Wait till read actually starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (wait_uwire_csr_flag(RDRB | CSRB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RDRB, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto eio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* rx bit 0 is last received; multibyte words will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * be properly byteswapped on the way to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val = uwire_read_reg(UWIRE_RDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val &= (1 << bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *buf++ = (u8) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (bytes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *buf++ = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) status += bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_debug("%s: read-%d =%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_name(&spi->dev), bits, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) eio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct uwire_state *ust = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct uwire_spi *uwire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int div1_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uwire = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* mode 0..3, clock inverted separately;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * standard nCS signaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * don't treat DI=high as "not ready"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) flags |= UWIRE_CS_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) flags |= UWIRE_CLK_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case SPI_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case SPI_MODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case SPI_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case SPI_MODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* assume it's already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rate = clk_get_rate(uwire->ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (t != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* F_INT = mpu_xor_clk / DIV1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (div1_idx = 0; div1_idx < 4; div1_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) switch (div1_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) div1 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) div1 = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) div1 = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) div1 = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) div2 = (rate / div1 + hz - 1) / hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (div2 <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (div1_idx == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pr_debug("%s: lowest clock %ld, need %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_name(&spi->dev), rate / 10 / 8, hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) status = -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* we have to cache this and reset in uwire_chipselect as this is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * global parameter and another uwire device can change it under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ust->div1_idx = div1_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uwire_set_clk1_div(div1_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rate /= div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch (div2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) flags |= UWIRE_FREQ_DIV_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) flags |= UWIRE_FREQ_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rate /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) flags |= UWIRE_FREQ_DIV_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) rate /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) omap_uwire_configure_mode(spi->chip_select, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __func__, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_get_rate(uwire->ck) / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int uwire_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct uwire_state *ust = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bool initial_setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ust == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ust = kzalloc(sizeof(*ust), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ust == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spi->controller_state = ust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) initial_setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) status = uwire_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (status && initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) kfree(ust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void uwire_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) kfree(spi->controller_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void uwire_off(struct uwire_spi *uwire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uwire_write_reg(UWIRE_SR3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_disable_unprepare(uwire->ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spi_master_put(uwire->bitbang.master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int uwire_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct uwire_spi *uwire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) master = spi_alloc_master(&pdev->dev, sizeof *uwire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uwire = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!uwire_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) platform_set_drvdata(pdev, uwire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uwire->ck = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (IS_ERR(uwire->ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) status = PTR_ERR(uwire->ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_dbg(&pdev->dev, "no functional clock?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk_prepare_enable(uwire->ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uwire_idx_shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uwire_idx_shift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uwire_write_reg(UWIRE_SR3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) master->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) master->bus_num = 2; /* "official" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) master->setup = uwire_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) master->cleanup = uwire_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uwire->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uwire->bitbang.chipselect = uwire_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uwire->bitbang.setup_transfer = uwire_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uwire->bitbang.txrx_bufs = uwire_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) status = spi_bitbang_start(&uwire->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uwire_off(uwire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int uwire_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct uwire_spi *uwire = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) // FIXME remove all child devices, somewhere ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spi_bitbang_stop(&uwire->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) uwire_off(uwire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_ALIAS("platform:omap_uwire");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct platform_driver uwire_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "omap_uwire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .probe = uwire_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .remove = uwire_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) // suspend ... unuse ck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) // resume ... use ck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int __init omap_uwire_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* FIXME move these into the relevant board init code. also, include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * H3 support; it uses tsc2101 like H2 (on a different chipselect).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (machine_is_omap_h2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* defaults: W21 SDO, U18 SDI, V19 SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) omap_cfg_reg(N14_1610_UWIRE_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) omap_cfg_reg(N15_1610_UWIRE_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (machine_is_omap_perseus2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return platform_driver_register(&uwire_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void __exit omap_uwire_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) platform_driver_unregister(&uwire_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) subsys_initcall(omap_uwire_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_exit(omap_uwire_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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