^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP7xx SPI 100k controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Fabrice Crohas <fcrohas@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * from original omap1_mcspi driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005, 2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Juha Yrj�l� <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP1_SPI100K_MAX_FREQ 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_SETUP1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_SETUP2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_TX_LSB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_TX_MSB 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_RX_LSB 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_RX_MSB 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPI_CTRL_SEN(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPI_CTRL_WR (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_CTRL_RD (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPI_STATUS_WE (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_STATUS_RD (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * cache operations; better heuristics consider wordsize and bitrate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA_MIN_BYTES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPI_RUNNING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_SHUTDOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct omap1_spi100k {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk *fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Virtual base address of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct omap1_spi100k_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void spi100k_enable_clock(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* enable SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = readw(spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val |= SPI_SETUP1_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writew(val, spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void spi100k_disable_clock(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* disable SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = readw(spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val &= ~SPI_SETUP1_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writew(val, spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void spi100k_write_data(struct spi_master *master, int len, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* write 16-bit word, shifting 8-bit data if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (len <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spi100k_enable_clock(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writew(data , spi100k->base + SPI_TX_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writew(SPI_CTRL_SEN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SPI_CTRL_WORD_SIZE(len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SPI_CTRL_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spi100k->base + SPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Wait for bit ack send change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spi100k_disable_clock(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int spi100k_read_data(struct spi_master *master, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int dataL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Always do at least 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (len <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spi100k_enable_clock(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writew(SPI_CTRL_SEN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SPI_CTRL_WORD_SIZE(len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SPI_CTRL_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spi100k->base + SPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dataL = readw(spi100k->base + SPI_RX_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) readw(spi100k->base + SPI_RX_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spi100k_disable_clock(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return dataL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void spi100k_open(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* get control of SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writew(SPI_SETUP1_INT_READ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SPI_SETUP1_INT_WRITE_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* configure clock and interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SPI_SETUP2_NEGATIVE_LEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writew(0x05fc, spi100k->base + SPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writew(0x05fd, spi100k->base + SPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct omap1_spi100k_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int count, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) count = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) c = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) word_len = cs->word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (word_len <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const u8 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) c -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (xfer->tx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spi100k_write_data(spi->master, word_len, *tx++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (xfer->rx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *rx++ = spi100k_read_data(spi->master, word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } while (c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else if (word_len <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const u16 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) c -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (xfer->tx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spi100k_write_data(spi->master, word_len, *tx++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (xfer->rx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *rx++ = spi100k_read_data(spi->master, word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } while (c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else if (word_len <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const u32 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) rx = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tx = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) c -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (xfer->tx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spi100k_write_data(spi->master, word_len, *tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (xfer->rx_buf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *rx = spi100k_read_data(spi->master, word_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } while (c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return count - c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* called only when no transfer is active to this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int omap1_spi100k_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct omap1_spi100k_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (t != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) word_len = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) word_len = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (word_len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cs->word_len = word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* SPI init before transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writew(0x3e , spi100k->base + SPI_SETUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writew(0x00 , spi100k->base + SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writew(0x3e , spi100k->base + SPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int omap1_spi100k_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct omap1_spi100k *spi100k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct omap1_spi100k_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spi100k = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cs->base = spi100k->base + spi->chip_select * 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spi100k_open(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk_prepare_enable(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk_prepare_enable(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = omap1_spi100k_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk_disable_unprepare(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_disable_unprepare(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int omap1_spi100k_transfer_one_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct spi_transfer *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int cs_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) status = omap1_spi100k_setup_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!cs_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) omap1_spi100k_force_cs(spi100k, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cs_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) count = omap1_spi100k_txrx_pio(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) m->actual_length += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (count != t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* ignore the "leave it on after last xfer" hint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (t->cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) omap1_spi100k_force_cs(spi100k, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cs_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) status = omap1_spi100k_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (cs_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) omap1_spi100k_force_cs(spi100k, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int omap1_spi100k_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct omap1_spi100k *spi100k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!pdev->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_dbg(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (pdev->id != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) master->setup = omap1_spi100k_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) master->transfer_one_message = omap1_spi100k_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) master->num_chipselect = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) master->mode_bits = MODEBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * The memory region base address is taken as the platform_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * You should allocate this with ioremap() before initializing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * the SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spi100k->ick = devm_clk_get(&pdev->dev, "ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (IS_ERR(spi100k->ick)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) status = PTR_ERR(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spi100k->fck = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (IS_ERR(spi100k->fck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) status = PTR_ERR(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) status = clk_prepare_enable(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) status = clk_prepare_enable(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto err_ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) status = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto err_fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err_fck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_disable_unprepare(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) err_ick:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk_disable_unprepare(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int omap1_spi100k_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) clk_disable_unprepare(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clk_disable_unprepare(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int omap1_spi100k_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) clk_disable_unprepare(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk_disable_unprepare(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int omap1_spi100k_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = clk_prepare_enable(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(dev, "Failed to enable ick: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = clk_prepare_enable(spi100k->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(dev, "Failed to enable fck: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk_disable_unprepare(spi100k->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct dev_pm_ops omap1_spi100k_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) omap1_spi100k_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct platform_driver omap1_spi100k_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .name = "omap1_spi100k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .pm = &omap1_spi100k_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .probe = omap1_spi100k_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .remove = omap1_spi100k_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) module_platform_driver(omap1_spi100k_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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