^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * NXP FlexSPI(FSPI) controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2019-2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2020 Puresoftware Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * FlexSPI is a flexsible SPI host controller which supports two SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * channels and up to 4 external devices. Each channel supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * data lines).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * FlexSPI controller is driven by the LUT(Look-up Table) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * LUT registers are a look-up-table for sequences of instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * A valid sequence consists of four LUT registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Maximum 32 LUT sequences can be programmed simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * LUTs are being created at run-time based on the commands passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * from the spi-mem framework, thus using single LUT index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Software triggered Flash read/write access by IP Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Memory mapped read access by AHB Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Based on SPI MEM interface and spi-fsl-qspi.c driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Boris Brezillon <bbrezillon@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Frieder Schrempf <frieder.schrempf@kontron.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The driver only uses one single LUT entry, that is updated on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * each call of exec_op(). Index 0 is preset at boot with a basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * read operation, so let's use the last entry (31).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SEQID_LUT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Registers used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FSPI_MCR0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FSPI_MCR0_LEARN_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FSPI_MCR0_SCRFRUN_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FSPI_MCR0_OCTCOMB_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FSPI_MCR0_DOZE_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FSPI_MCR0_HSEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FSPI_MCR0_SERCLKDIV BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FSPI_MCR0_ATDF_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FSPI_MCR0_ARDF_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FSPI_MCR0_END_CFG(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FSPI_MCR0_MDIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FSPI_MCR0_SWRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FSPI_MCR1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FSPI_MCR2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FSPI_MCR2_CLRLRPHS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FSPI_MCR2_ABRDATSZ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FSPI_MCR2_ABRLEARN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FSPI_MCR2_ABR_READ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FSPI_MCR2_ABRWRITE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FSPI_MCR2_ABRDUMMY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FSPI_MCR2_ABR_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FSPI_MCR2_ABRCADDR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FSPI_MCR2_ABRRADDR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FSPI_MCR2_ABR_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FSPI_AHBCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FSPI_AHBCR_RDADDROPT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FSPI_AHBCR_PREF_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FSPI_AHBCR_BUFF_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FSPI_AHBCR_CACH_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FSPI_AHBCR_CLRTXBUF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FSPI_AHBCR_CLRRXBUF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FSPI_AHBCR_PAR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FSPI_INTEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FSPI_INTEN_SCLKSBWR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FSPI_INTEN_SCLKSBRD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FSPI_INTEN_DATALRNFL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FSPI_INTEN_IPTXWE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FSPI_INTEN_IPRXWA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FSPI_INTEN_AHBCMDERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FSPI_INTEN_IPCMDERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FSPI_INTEN_AHBCMDGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FSPI_INTEN_IPCMDGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FSPI_INTEN_IPCMDDONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FSPI_INTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FSPI_INTR_SCLKSBWR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FSPI_INTR_SCLKSBRD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FSPI_INTR_DATALRNFL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FSPI_INTR_IPTXWE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FSPI_INTR_IPRXWA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FSPI_INTR_AHBCMDERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FSPI_INTR_IPCMDERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FSPI_INTR_AHBCMDGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FSPI_INTR_IPCMDGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FSPI_INTR_IPCMDDONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FSPI_LUTKEY 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FSPI_LUTKEY_VALUE 0x5AF05AF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FSPI_LCKCR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FSPI_LCKER_LOCK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FSPI_LCKER_UNLOCK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FSPI_BUFXCR_INVALID_MSTRID 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FSPI_AHBRX_BUF0CR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FSPI_AHBRX_BUF1CR0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FSPI_AHBRX_BUF2CR0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FSPI_AHBRX_BUF3CR0 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FSPI_AHBRX_BUF4CR0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FSPI_AHBRX_BUF5CR0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FSPI_AHBRX_BUF6CR0 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FSPI_AHBRX_BUF7CR0 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FSPI_AHBRX_BUF0CR1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FSPI_AHBRX_BUF1CR1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FSPI_AHBRX_BUF2CR1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FSPI_AHBRX_BUF3CR1 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FSPI_AHBRX_BUF4CR1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FSPI_AHBRX_BUF5CR1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FSPI_AHBRX_BUF6CR1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FSPI_AHBRX_BUF7CR1 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FSPI_FLSHA1CR0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FSPI_FLSHA2CR0 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FSPI_FLSHB1CR0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FSPI_FLSHB2CR0 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FSPI_FLSHXCR0_SZ_KB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FSPI_FLSHA1CR1 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FSPI_FLSHA2CR1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FSPI_FLSHB1CR1 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FSPI_FLSHB2CR1 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FSPI_FLSHXCR1_WA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FSPI_FLSHXCR1_TCSS(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FSPI_FLSHA1CR2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FSPI_FLSHA2CR2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FSPI_FLSHB1CR2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FSPI_FLSHB2CR2 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FSPI_FLSHXCR2_CLRINSP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FSPI_IPCR0 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FSPI_IPCR1 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FSPI_IPCR1_IPAREN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FSPI_IPCR1_SEQNUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FSPI_IPCR1_SEQID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FSPI_IPCR1_IDATSZ(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FSPI_IPCMD 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FSPI_IPCMD_TRG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FSPI_DLPR 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FSPI_IPRXFCR 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FSPI_IPRXFCR_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FSPI_IPRXFCR_DMA_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define FSPI_IPTXFCR 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define FSPI_IPTXFCR_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define FSPI_IPTXFCR_DMA_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FSPI_DLLACR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define FSPI_DLLACR_OVRDEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FSPI_DLLBCR 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FSPI_DLLBCR_OVRDEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FSPI_STS0 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define FSPI_STS0_DLPHB(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define FSPI_STS0_DLPHA(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FSPI_STS0_ARB_IDLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FSPI_STS0_SEQ_IDLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FSPI_STS1 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FSPI_STS1_AHB_ERRID(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FSPI_AHBSPNST 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define FSPI_AHBSPNST_ACTIVE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FSPI_IPRXFSTS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define FSPI_IPRXFSTS_FILL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define FSPI_IPTXFSTS 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FSPI_IPTXFSTS_FILL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FSPI_RFDR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FSPI_TFDR 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define FSPI_LUT_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FSPI_LUT_REG(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* register map end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Instruction set for the LUT register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LUT_STOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LUT_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define LUT_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define LUT_CADDR_SDR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LUT_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define LUT_MODE2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define LUT_MODE4 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define LUT_MODE8 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LUT_NXP_WRITE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define LUT_NXP_READ 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define LUT_LEARN_SDR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define LUT_DATSZ_SDR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LUT_DUMMY 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LUT_DUMMY_RWDS_SDR 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define LUT_JMP_ON_CS 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define LUT_CMD_DDR 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LUT_ADDR_DDR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LUT_CADDR_DDR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LUT_MODE_DDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LUT_MODE2_DDR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LUT_MODE4_DDR 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LUT_MODE8_DDR 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define LUT_WRITE_DDR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LUT_READ_DDR 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define LUT_LEARN_DDR 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define LUT_DATSZ_DDR 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define LUT_DUMMY_DDR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define LUT_DUMMY_RWDS_DDR 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Calculate number of required PAD bits for LUT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * The pad stands for the number of IO lines [0:7].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * For example, the octal read needs eight IO lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * so you should use LUT_PAD(8). This macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * returns 3 i.e. use eight (2^3) IP lines for read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LUT_PAD(x) (fls(x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Macro for constructing the LUT entries with the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * ---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * ---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PAD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define INSTR_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OPRND_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Macros for constructing the LUT register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LUT_DEF(idx, ins, pad, opr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (opr)) << (((idx) % 2) * OPRND_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define POLL_TOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define NXP_FSPI_MAX_CHIPSELECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define NXP_FSPI_MIN_IOMAP SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct nxp_fspi_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int rxfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int txfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int ahb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bool little_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct nxp_fspi_devtype_data lx2160a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .rxfifo = SZ_512, /* (64 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .txfifo = SZ_1K, /* (128 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .quirks = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .little_endian = true, /* little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct nxp_fspi_devtype_data imx8mm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .rxfifo = SZ_512, /* (64 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .txfifo = SZ_1K, /* (128 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .quirks = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .little_endian = true, /* little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct nxp_fspi_devtype_data imx8qxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .rxfifo = SZ_512, /* (64 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .txfifo = SZ_1K, /* (128 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .quirks = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .little_endian = true, /* little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct nxp_fspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void __iomem *ahb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 memmap_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 memmap_phy_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 memmap_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 memmap_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct clk *clk, *clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct completion c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) const struct nxp_fspi_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int selected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * R/W functions for big- or little-endian registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * The FSPI controller's endianness is independent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * the CPU core's endianness. So far, although the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * core is little-endian the FSPI controller can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * big-endian or little-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (f->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (f->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct nxp_fspi *f = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) reg = fspi_readl(f, f->iobase + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (reg & FSPI_INTR_IPCMDDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) complete(&f->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static bool nxp_fspi_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (op->dummy.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (op->data.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * The number of address bytes should be equal to or less than 4 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (op->addr.nbytes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * If requested address value is greater than controller assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * memory mapped space, return error as it didn't fit in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * of assigned address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (op->addr.val >= f->memmap_phy_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Max 64 dummy clock cycles supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (op->dummy.buswidth &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Max data length, check controller limits and alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (op->data.dir == SPI_MEM_DATA_IN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (op->data.nbytes > f->devtype_data->ahb_buf_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) !IS_ALIGNED(op->data.nbytes, 8))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (op->data.dir == SPI_MEM_DATA_OUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) op->data.nbytes > f->devtype_data->txfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return spi_mem_default_supports_op(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Instead of busy looping invoke readl_poll_timeout functionality. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 mask, u32 delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 timeout_us, bool c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!f->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mask = (u32)cpu_to_be32(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return readl_poll_timeout(base, reg, (reg & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) delay_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return readl_poll_timeout(base, reg, !(reg & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) delay_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * If the slave device content being changed by Write/Erase, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * invalidate the AHB buffer. This can be achieved by doing the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * of controller after setting MCR0[SWRESET] bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline void nxp_fspi_invalid(struct nxp_fspi *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reg = fspi_readl(f, f->iobase + FSPI_MCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* w1c register, wait unit clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void __iomem *base = f->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 lutval[4] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int lutidx = 1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) op->cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* addr bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) LUT_PAD(op->addr.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) op->addr.nbytes * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* dummy bytes, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (op->dummy.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Due to FlexSPI controller limitation number of PAD for dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * buswidth needs to be programmed as equal to data buswidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) LUT_PAD(op->data.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) op->dummy.nbytes * 8 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* read/write data bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) lutval[lutidx / 2] |= LUT_DEF(lutidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) op->data.dir == SPI_MEM_DATA_IN ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) LUT_NXP_READ : LUT_NXP_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) LUT_PAD(op->data.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* stop condition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* unlock LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* fill LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < ARRAY_SIZE(lutval); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* lock LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (is_acpi_node(f->dev->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = clk_prepare_enable(f->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = clk_prepare_enable(f->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk_disable_unprepare(f->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (is_acpi_node(f->dev->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) clk_disable_unprepare(f->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) clk_disable_unprepare(f->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * register and start base address of the slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * (Higher address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * -------- <-- FLSHB2CR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * | B2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * B2 start address --> -------- <-- FLSHB1CR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * | B1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * B1 start address --> -------- <-- FLSHA2CR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * | A2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * A2 start address --> -------- <-- FLSHA1CR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * | A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * A1 start address --> -------- (Lower address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Start base address defines the starting address range for given CS and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * But, different targets are having different combinations of number of CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * some targets only have single CS or two CS covering controller's full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * memory mapped space area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Thus, implementation is being done as independent of the size and number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * of the connected slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Assign controller memory mapped space size as the size to the connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * chip-select Flash configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * memory mapped size of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Value for rest of the CS FLSHxxCR0 register would be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned long rate = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint64_t size_kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Return, if previously selected slave device is same as current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * requested slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (f->selected == spi->chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Reset FLSHxxCR0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Assign controller memory mapped space as size, KBytes, of flash. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 4 * spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) nxp_fspi_clk_disable_unprep(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = clk_set_rate(f->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = nxp_fspi_clk_prep_enable(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) f->selected = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 start = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* if necessary, ioremap before AHB read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if ((!f->ahb_addr) || start < f->memmap_start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) start + len > f->memmap_start + f->memmap_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (f->ahb_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) iounmap(f->ahb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) f->memmap_start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) len : NXP_FSPI_MIN_IOMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) f->memmap_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!f->ahb_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(f->dev, "failed to alloc memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Read out the data directly from the AHB buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) memcpy_fromio(op->data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) f->ahb_addr + start - f->memmap_start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) void __iomem *base = f->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 *buf = (u8 *) op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* clear the TX FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Default value of water mark level is 8 bytes, hence in single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * write request controller can write max 8 bytes of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Wait for TXFIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) FSPI_INTR_IPTXWE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) POLL_TOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (i < op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Wait for TXFIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) FSPI_INTR_IPTXWE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) POLL_TOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) memcpy(&data, buf + i + j, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) fspi_writel(f, data, base + FSPI_TFDR + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void __iomem *base = f->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u8 *buf = (u8 *) op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Default value of water mark level is 8 bytes, hence in single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * read request controller can read max 8 bytes of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Wait for RXFIFO available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) FSPI_INTR_IPRXWA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) POLL_TOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* move the FIFO pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (i < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int size, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) buf = op->data.buf.in + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Wait for RXFIFO available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) FSPI_INTR_IPRXWA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) POLL_TOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) len = op->data.nbytes - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (j = 0; j < op->data.nbytes - i; j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) tmp = fspi_readl(f, base + FSPI_RFDR + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) size = min(len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) memcpy(buf + j, &tmp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) len -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* invalid the RXFIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* move the FIFO pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void __iomem *base = f->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int seqnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) reg = fspi_readl(f, base + FSPI_IPRXFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* invalid RXFIFO first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) reg &= ~FSPI_IPRXFCR_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) reg = reg | FSPI_IPRXFCR_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) fspi_writel(f, reg, base + FSPI_IPRXFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) init_completion(&f->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * Always start the sequence at the same index since we update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * the LUT at each exec_op() call. And also specify the DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * length, since it's has not been specified in the LUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fspi_writel(f, op->data.nbytes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) base + FSPI_IPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Trigger the LUT now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Wait for the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Invoke IP data read, if request is of data read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) nxp_fspi_read_rxfifo(f, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&f->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Wait for controller being ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) WARN_ON(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) nxp_fspi_select_mem(f, mem->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) nxp_fspi_prepare_lut(f, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * If we have large chunks of data, we read them through the AHB bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * by accessing the mapped memory. In all other cases we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * IP commands to access the flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) err = nxp_fspi_read_ahb(f, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) nxp_fspi_fill_txfifo(f, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) err = nxp_fspi_do_op(f, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Invalidate the data in the AHB buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) nxp_fspi_invalid(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mutex_unlock(&f->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (op->data.dir == SPI_MEM_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (op->data.nbytes > f->devtype_data->txfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) op->data.nbytes = f->devtype_data->txfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (op->data.nbytes > f->devtype_data->ahb_buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) op->data.nbytes = f->devtype_data->ahb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int nxp_fspi_default_setup(struct nxp_fspi *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void __iomem *base = f->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* disable and unprepare clock to avoid glitch pass to controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) nxp_fspi_clk_disable_unprep(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* the default frequency, we will change it later if necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = clk_set_rate(f->clk, 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = nxp_fspi_clk_prep_enable(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Reset the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* w1c register, wait unit clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Disable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Reset the DLL register to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* enable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) base + FSPI_MCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Disable same device enable bit and configure all slave devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) reg = fspi_readl(f, f->iobase + FSPI_MCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) fspi_writel(f, reg, base + FSPI_MCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* AHB configuration for access buffer 0~7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * Set ADATSZ with the maximum AHB buffer size to improve the read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* prefetch and no start address alignment limitation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) base + FSPI_AHBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* AHB Read - Set lut sequence ID for all CS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) f->selected = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* enable the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const char *nxp_fspi_get_name(struct spi_mem *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct device *dev = &mem->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) // Set custom name derived from the platform_device of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (of_get_available_child_count(f->dev->of_node) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return dev_name(f->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) name = devm_kasprintf(dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "%s-%d", dev_name(f->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mem->spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev_err(dev, "failed to get memory for custom flash name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .adjust_op_size = nxp_fspi_adjust_op_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .supports_op = nxp_fspi_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .exec_op = nxp_fspi_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .get_name = nxp_fspi_get_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int nxp_fspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct nxp_fspi *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ctlr = spi_alloc_master(&pdev->dev, sizeof(*f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) f = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) f->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) f->devtype_data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!f->devtype_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) platform_set_drvdata(pdev, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* find the resources - configuration register address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (is_acpi_node(f->dev->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) IORESOURCE_MEM, "fspi_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) f->iobase = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (IS_ERR(f->iobase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = PTR_ERR(f->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* find the resources - controller memory mapped space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (is_acpi_node(f->dev->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) IORESOURCE_MEM, "fspi_mmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* assign memory mapped starting address and mapped size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) f->memmap_phy = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) f->memmap_phy_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* find the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (dev_of_node(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) f->clk_en = devm_clk_get(dev, "fspi_en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (IS_ERR(f->clk_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ret = PTR_ERR(f->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) f->clk = devm_clk_get(dev, "fspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (IS_ERR(f->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = PTR_ERR(f->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = nxp_fspi_clk_prep_enable(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_err(dev, "can not enable the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Clear potential interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) reg = fspi_readl(f, f->iobase + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fspi_writel(f, reg, f->iobase + FSPI_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* find the irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = devm_request_irq(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) nxp_fspi_irq_handler, 0, pdev->name, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(dev, "failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) mutex_init(&f->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ctlr->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ctlr->mem_ops = &nxp_fspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) nxp_fspi_default_setup(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ctlr->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = devm_spi_register_controller(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mutex_destroy(&f->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) nxp_fspi_clk_disable_unprep(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) err_put_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dev_err(dev, "NXP FSPI probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int nxp_fspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct nxp_fspi *f = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* disable the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) nxp_fspi_clk_disable_unprep(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mutex_destroy(&f->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (f->ahb_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) iounmap(f->ahb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static int nxp_fspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int nxp_fspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct nxp_fspi *f = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) nxp_fspi_default_setup(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const struct of_device_id nxp_fspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const struct acpi_device_id nxp_fspi_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct dev_pm_ops nxp_fspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .suspend = nxp_fspi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .resume = nxp_fspi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static struct platform_driver nxp_fspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .name = "nxp-fspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .of_match_table = nxp_fspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .pm = &nxp_fspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .probe = nxp_fspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .remove = nxp_fspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) module_platform_driver(nxp_fspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) MODULE_DESCRIPTION("NXP FSPI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) MODULE_AUTHOR("NXP Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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