^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct npcm_pspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bool is_save_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_NAME "npcm-pspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NPCM_PSPI_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM_PSPI_CTL1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPCM_PSPI_STAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* definitions for control and status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM_PSPI_CTL1_SPIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM_PSPI_CTL1_MOD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM_PSPI_CTL1_EIR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPCM_PSPI_CTL1_EIW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPCM_PSPI_CTL1_SCM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPCM_PSPI_CTL1_SCIDL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPCM_PSPI_STAT_BSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NPCM_PSPI_STAT_RBF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* general definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NPCM_PSPI_TIMEOUT_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NPCM_PSPI_MAX_CLK_DIVIDER 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NPCM_PSPI_MIN_CLK_DIVIDER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NPCM_PSPI_DEFAULT_CLK 25000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline unsigned int bytes_per_word(unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return bits <= 8 ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = ioread16(priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite16(val, priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val = ioread16(priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) iowrite16(val, priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline void npcm_pspi_enable(struct npcm_pspi *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = ioread16(priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val |= NPCM_PSPI_CTL1_SPIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) iowrite16(val, priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void npcm_pspi_disable(struct npcm_pspi *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = ioread16(priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val &= ~NPCM_PSPI_CTL1_SPIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iowrite16(val, priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void npcm_pspi_set_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 mode_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case SPI_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mode_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case SPI_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mode_val = NPCM_PSPI_CTL1_SCIDL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case SPI_MODE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mode_val = NPCM_PSPI_CTL1_SCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case SPI_MODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) regtemp &= ~NPCM_PSPI_CTL1_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regtemp |= NPCM_PSPI_CTL1_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 ckdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 regtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* the supported rates are numbers from 4 to 256. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void npcm_pspi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) priv->tx_buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) priv->rx_buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) priv->tx_bytes = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) priv->rx_bytes = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!priv->is_save_param || priv->mode != spi->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) npcm_pspi_set_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) priv->mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * If transfer is even length, and 8 bits per word transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * then implement 16 bits-per-word transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (priv->bits_per_word == 8 && !(t->len & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) t->bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) npcm_pspi_set_transfer_size(priv, t->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) npcm_pspi_set_baudrate(priv, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) priv->speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!priv->is_save_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) priv->is_save_param = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void npcm_pspi_send(struct npcm_pspi *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) priv->tx_bytes -= wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!priv->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (wsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = *priv->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iowrite8(val, NPCM_PSPI_DATA + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = *priv->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val = *priv->tx_buf++ | (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) iowrite16(val, NPCM_PSPI_DATA + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void npcm_pspi_recv(struct npcm_pspi *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->rx_bytes -= rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!priv->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) switch (rsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *priv->rx_buf++ = ioread8(priv->base + NPCM_PSPI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val = ioread16(priv->base + NPCM_PSPI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *priv->rx_buf++ = (val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *priv->rx_buf++ = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int npcm_pspi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct npcm_pspi *priv = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) npcm_pspi_setup_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reinit_completion(&priv->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) npcm_pspi_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) status = wait_for_completion_timeout(&priv->xfer_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) msecs_to_jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (NPCM_PSPI_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) npcm_pspi_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct npcm_pspi *priv = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct npcm_pspi *priv = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reset_control_assert(priv->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reset_control_deassert(priv->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct npcm_pspi *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) stat = ioread8(priv->base + NPCM_PSPI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!priv->tx_buf && !priv->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (priv->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (stat & NPCM_PSPI_STAT_RBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ioread8(NPCM_PSPI_DATA + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (priv->tx_bytes == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) npcm_pspi_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) complete(&priv->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if ((stat & NPCM_PSPI_STAT_BSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (priv->tx_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) npcm_pspi_send(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (priv->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (stat & NPCM_PSPI_STAT_RBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!priv->rx_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) npcm_pspi_recv(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!priv->rx_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) npcm_pspi_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) complete(&priv->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int npcm_pspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct npcm_pspi *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) master = spi_alloc_master(&pdev->dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) priv = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) priv->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) priv->is_save_param = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (IS_ERR(priv->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) priv->reset = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (IS_ERR(priv->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = PTR_ERR(priv->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* reset SPI-HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) npcm_pspi_reset_hw(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "npcm-pspi", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(&pdev->dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) init_completion(&priv->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clk_hz = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) master->mode_bits = SPI_CPHA | SPI_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) master->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) master->transfer_one = npcm_pspi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) master->prepare_transfer_hardware =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) npcm_pspi_prepare_transfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) master->unprepare_transfer_hardware =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) npcm_pspi_unprepare_transfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* set to default clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) out_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) out_master_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int npcm_pspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct npcm_pspi *priv = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) npcm_pspi_reset_hw(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct of_device_id npcm_pspi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .compatible = "nuvoton,npcm750-pspi", .data = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_DEVICE_TABLE(of, npcm_pspi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct platform_driver npcm_pspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .of_match_table = npcm_pspi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .probe = npcm_pspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .remove = npcm_pspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) module_platform_driver(npcm_pspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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