^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale MXS SPI master driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2012 DENX Software Engineering, GmbH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Rework and transition to new API by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // Based on previous attempt by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // Fabio Estevam <fabio.estevam@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) // Based on code from U-Boot bootloader by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) // Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) // Based on spi-stmp.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) // Author: Dmitry Pervushin <dimka@embeddedalley.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/spi/mxs-spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <trace/events/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_NAME "mxs-spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Use 10S timeout for very long transfers, it should suffice. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SSP_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SG_MAXLEN 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Flags for txrx functions. More efficient that using an argument register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * each one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TXRX_WRITE (1<<0) /* This is a write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mxs_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mxs_ssp ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct completion c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int sck; /* Rate requested (vs actual) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int mxs_spi_setup_transfer(struct spi_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mxs_spi *spi = spi_master_get_devdata(dev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (hz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (hz != spi->sck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mxs_ssp_set_clk_rate(ssp, hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Save requested rate, hz, rather than the actual rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * ssp->clk_rate. Otherwise we would set the rate every transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * when the actual rate is not quite the same as requested rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spi->sck = hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Perhaps we should return an error if the actual clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * nowhere close to what was requested?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(BM_SSP_CTRL0_LOCK_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ssp->base + HW_SSP_CTRL1(ssp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(0x0, ssp->base + HW_SSP_CMD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(0x0, ssp->base + HW_SSP_CMD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static u32 mxs_spi_cs_to_reg(unsigned cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * in HW_SSP_CTRL0 register do have multiple usage, please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * the datasheet for further details. In SPI mode, they are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * toggle the chip-select lines (nCS pins).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (cs & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (cs & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = readl_relaxed(ssp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = ~reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (reg == mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void mxs_ssp_dma_irq_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mxs_spi *spi = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) complete(&spi->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mxs_ssp *ssp = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __func__, __LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) readl(ssp->base + HW_SSP_CTRL1(ssp)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) readl(ssp->base + HW_SSP_STATUS(ssp)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int mxs_spi_txrx_dma(struct mxs_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned char *buf, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct dma_async_tx_descriptor *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const bool vmalloced_buf = is_vmalloc_addr(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const int sgs = DIV_ROUND_UP(len, desc_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int min, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct page *vm_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 pio[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } *dma_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!dma_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reinit_completion(&spi->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Chip select was already programmed into CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BM_SSP_CTRL0_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!(flags & TXRX_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ctrl0 |= BM_SSP_CTRL0_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Queue the DMA data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (sg_count = 0; sg_count < sgs; sg_count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Prepare the transfer descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) min = min(len, desc_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * De-assert CS on last segment if flag is set (i.e., no more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * transfers will follow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ssp->devid == IMX23_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ctrl0 |= min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dma_xfer[sg_count].pio[0] = ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dma_xfer[sg_count].pio[3] = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (vmalloced_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) vm_page = vmalloc_to_page(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!vm_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto err_vmalloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sg_init_table(&dma_xfer[sg_count].sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sg_set_page(&dma_xfer[sg_count].sg, vm_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) min, offset_in_page(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sg_init_one(&dma_xfer[sg_count].sg, buf, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) len -= min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) buf += min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Queue the PIO register write transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) desc = dmaengine_prep_slave_sg(ssp->dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (struct scatterlist *)dma_xfer[sg_count].pio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (ssp->devid == IMX23_SSP) ? 1 : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DMA_TRANS_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sg_count ? DMA_PREP_INTERRUPT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "Failed to get PIO reg. write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto err_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) desc = dmaengine_prep_slave_sg(ssp->dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) &dma_xfer[sg_count].sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_err(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "Failed to get DMA data write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto err_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * The last descriptor must have this callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * to finish the DMA transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) desc->callback = mxs_ssp_dma_irq_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) desc->callback_param = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Start the transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dma_async_issue_pending(ssp->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!wait_for_completion_timeout(&spi->c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msecs_to_jiffies(SSP_TIMEOUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(ssp->dev, "DMA transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dmaengine_terminate_all(ssp->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto err_vmalloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) err_vmalloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) while (--sg_count >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err_mapped:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) kfree(dma_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int mxs_spi_txrx_pio(struct mxs_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned char *buf, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) writel(BM_SSP_CTRL0_IGNORE_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (len == 0 && (flags & TXRX_DEASSERT_CS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel(BM_SSP_CTRL0_IGNORE_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ssp->devid == IMX23_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel(BM_SSP_CTRL0_XFER_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(1, ssp->base + HW_SSP_XFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (flags & TXRX_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(BM_SSP_CTRL0_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel(BM_SSP_CTRL0_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) writel(BM_SSP_CTRL0_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (flags & TXRX_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writel(*buf, ssp->base + HW_SSP_DATA(ssp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(BM_SSP_CTRL0_DATA_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!(flags & TXRX_WRITE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) BM_SSP_STATUS_FIFO_EMPTY, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int mxs_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mxs_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Program CS register bits here, it will be used for all transfers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel(mxs_spi_cs_to_reg(m->spi->chip_select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) trace_spi_transfer_start(m, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) status = mxs_spi_setup_transfer(m->spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* De-assert on last transfer, inverted by cs_change flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) TXRX_DEASSERT_CS : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Small blocks can be transfered via PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * Measured by empiric means:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * DMA only: 2.164808 seconds, 473.0KB/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Combined: 1.676276 seconds, 610.9KB/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (t->len < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(BM_SSP_CTRL1_DMA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ssp->base + HW_SSP_CTRL1(ssp) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (t->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) status = mxs_spi_txrx_pio(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (void *)t->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) t->len, flag | TXRX_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) status = mxs_spi_txrx_pio(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) t->rx_buf, t->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(BM_SSP_CTRL1_DMA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ssp->base + HW_SSP_CTRL1(ssp) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (t->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) status = mxs_spi_txrx_dma(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (void *)t->tx_buf, t->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) flag | TXRX_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) status = mxs_spi_txrx_dma(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) t->rx_buf, t->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) trace_spi_transfer_stop(m, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) stmp_reset_block(ssp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int mxs_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct mxs_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret2 = clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret, ret2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int mxs_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mxs_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct mxs_ssp *ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int __maybe_unused mxs_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return mxs_spi_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int __maybe_unused mxs_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = mxs_spi_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0 && !pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) mxs_spi_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct dev_pm_ops mxs_spi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mxs_spi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct of_device_id mxs_spi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mxs_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) of_match_device(mxs_spi_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct mxs_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mxs_ssp *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int devid, clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int ret = 0, irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Default clock speed for the SPI core. 160MHz seems to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * work reasonably well with most SPI flashes, so use this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * as a default. Override with "clock-frequency" DT prop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) const int clk_freq_default = 160000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) irq_err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (irq_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) devid = (enum mxs_ssp_id) of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = of_property_read_u32(np, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clk_freq = clk_freq_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) master = spi_alloc_master(&pdev->dev, sizeof(*spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) master->transfer_one_message = mxs_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) master->mode_bits = SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) master->num_chipselect = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) master->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) master->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ssp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ssp->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ssp->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ssp->devid = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) init_completion(&spi->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_name(&pdev->dev), ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) goto out_master_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (IS_ERR(ssp->dmach)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(ssp->dev, "Failed to request DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = PTR_ERR(ssp->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto out_master_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pm_runtime_enable(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!pm_runtime_enabled(ssp->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = mxs_spi_runtime_resume(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(ssp->dev, "runtime resume failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) goto out_dma_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = pm_runtime_get_sync(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pm_runtime_put_noidle(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(ssp->dev, "runtime_get_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto out_pm_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_set_rate(ssp->clk, clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = stmp_reset_block(ssp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto out_pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto out_pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pm_runtime_put(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) out_pm_runtime_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pm_runtime_put(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) out_pm_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pm_runtime_disable(ssp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) out_dma_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dma_release_channel(ssp->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) out_master_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int mxs_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct mxs_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct mxs_ssp *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ssp = &spi->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mxs_spi_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dma_release_channel(ssp->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct platform_driver mxs_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .probe = mxs_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .remove = mxs_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .of_match_table = mxs_spi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .pm = &mxs_spi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) module_platform_driver(mxs_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_DESCRIPTION("MXS SPI master driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_ALIAS("platform:mxs-spi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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