^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2018 Macronix International Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Mason Yang <masonccyang@mxic.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // zhengxunli <zhengxunli@mxic.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Boris Brezillon <boris.brezillon@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HC_CFG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HC_CFG_IF_CFG(x) ((x) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HC_CFG_DUAL_SLAVE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HC_CFG_INDIVIDUAL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HC_CFG_NIO(x) (((x) / 4) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HC_CFG_TYPE_SPI_NOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HC_CFG_TYPE_SPI_NAND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HC_CFG_TYPE_SPI_RAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HC_CFG_TYPE_RAW_NAND 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HC_CFG_SLV_ACT(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HC_CFG_CLK_PH_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HC_CFG_CLK_POL_INV BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HC_CFG_BIG_ENDIAN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HC_CFG_DATA_PASS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HC_CFG_MAN_START_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HC_CFG_MAN_START BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HC_CFG_MAN_CS_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HC_CFG_MAN_CS_ASSERT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define INT_STS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define INT_STS_EN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define INT_SIG_EN 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INT_STS_ALL GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define INT_RDY_PIN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define INT_RDY_SR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define INT_LNR_SUSP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INT_ECC_ERR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INT_CRC_ERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define INT_LWR_DIS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INT_LRD_DIS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define INT_SDMA_INT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define INT_DMA_FINISH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define INT_RX_NOT_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define INT_RX_NOT_EMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define INT_TX_NOT_FULL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INT_TX_EMPTY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HC_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HC_EN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TXD(x) (0x14 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RXD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SS_CTRL(s) (0x30 + ((s) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LRD_CFG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LWR_CFG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RWW_CFG 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OP_READ BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OP_DUMMY_CYC(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OP_ADDR_BYTES(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OP_CMD_BYTES(x) (((x) - 1) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OP_OCTA_CRC_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OP_DQS_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OP_ENHC_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OP_PREAMBLE_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OP_DATA_DDR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OP_DATA_BUSW(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OP_ADDR_DDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OP_ADDR_BUSW(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OP_CMD_DDR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OP_CMD_BUSW(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OP_BUSW_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OP_BUSW_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OP_BUSW_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OP_BUSW_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OCTA_CRC 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ONFI_DIN_CNT(s) (0x3c + (s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LRD_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RWW_CTRL 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LWR_CTRL 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LMODE_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LMODE_SLV_ACT(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LMODE_CMD1(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LMODE_CMD0(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LRD_ADDR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LWR_ADDR 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LRD_RANGE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LWR_RANGE 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AXI_SLV_ADDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMAC_RD_CFG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DMAC_WR_CFG 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DMAC_CFG_PERIPH_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DMAC_CFG_ALLFLUSH_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DMAC_CFG_LASTFLUSH_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DMAC_CFG_QE(x) (((x) + 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DMAC_CFG_BURST_SZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DMAC_CFG_DIR_READ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DMAC_CFG_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMAC_RD_CNT 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMAC_WR_CNT 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDMA_ADDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DMAM_CFG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DMAM_CFG_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DMAM_CFG_CONT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DMAM_CFG_DIR_READ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DMAM_CFG_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DMAM_CNT 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LNR_TIMER_TH 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RDM_CFG0 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RDM_CFG0_POLY(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RDM_CFG1 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RDM_CFG1_RDM_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RDM_CFG1_SEED(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LWR_SUSP_CTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LWR_SUSP_CTRL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DMAS_CTRL 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DMAS_CTRL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DMAS_CTRL_DIR_READ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DATA_STROB 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DATA_STROB_EDO_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DATA_STROB_INV_POL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DATA_STROB_DELAY_2CYC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IDLY_CODE(x) (0xa4 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPIO 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPIO_PT(x) BIT(3 + ((x) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPIO_RESET(x) BIT(2 + ((x) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPIO_WPB(x) BIT((x) * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HC_VER 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HW_TEST(x) (0xe0 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mxic_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk *ps_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *send_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *send_dly_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 cur_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int mxic_spi_clk_enable(struct mxic_spi *mxic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = clk_prepare_enable(mxic->send_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = clk_prepare_enable(mxic->send_dly_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err_send_dly_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) err_send_dly_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_disable_unprepare(mxic->send_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void mxic_spi_clk_disable(struct mxic_spi *mxic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_disable_unprepare(mxic->send_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_disable_unprepare(mxic->send_dly_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel(IDLY_CODE_VAL(0, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IDLY_CODE_VAL(1, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IDLY_CODE_VAL(2, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IDLY_CODE_VAL(3, idly_code),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mxic->regs + IDLY_CODE(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(IDLY_CODE_VAL(4, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IDLY_CODE_VAL(5, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IDLY_CODE_VAL(6, idly_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IDLY_CODE_VAL(7, idly_code),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mxic->regs + IDLY_CODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = clk_set_rate(mxic->send_clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = clk_set_rate(mxic->send_dly_clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * A constant delay range from 0x0 ~ 0x1F for input delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * the unit is 78 ps, the max input delay is 2.418 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mxic_spi_set_input_delay_dqs(mxic, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Phase degree = 360 * freq * output-delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * where output-delay is a constant value 1 ns in FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Get Phase degree = 360 * freq * 1 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * = 360 * freq * 1 sec / 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * = 9 * freq / 25000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (mxic->cur_speed_hz == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mxic_spi_clk_disable(mxic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = mxic_spi_clk_setup(mxic, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = mxic_spi_clk_enable(mxic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mxic->cur_speed_hz = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void mxic_spi_hw_init(struct mxic_spi *mxic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel(0, mxic->regs + DATA_STROB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(0, mxic->regs + HC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(0, mxic->regs + LRD_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(0, mxic->regs + LRD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void *rxbuf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) while (pos < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int nbytes = len - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (nbytes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) nbytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (txbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) memcpy(&data, txbuf + pos, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(data, mxic->regs + TXD(nbytes % 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) sts & INT_RX_NOT_EMPTY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) data = readl(mxic->regs + RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) data >>= (8 * (4 - nbytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) memcpy(rxbuf + pos, &data, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pos += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) op->dummy.buswidth > 4 || op->cmd.buswidth > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (op->data.nbytes && op->dummy.nbytes &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) op->data.buswidth != op->dummy.buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (op->addr.nbytes > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return spi_mem_default_supports_op(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int mxic_spi_mem_exec_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int nio = 1, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 ss_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 opcode = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) nio = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) nio = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(HC_CFG_NIO(nio) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) HC_CFG_MAN_CS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(HC_EN_BIT, mxic->regs + HC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (op->dummy.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ss_ctrl |= OP_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for (i = 0; i < op->addr.nbytes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = mxic_spi_data_xfer(mxic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) op->data.dir == SPI_MEM_DATA_OUT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) op->data.buf.out : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) op->data.dir == SPI_MEM_DATA_IN ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) op->data.buf.in : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(0, mxic->regs + HC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .supports_op = mxic_spi_mem_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .exec_op = mxic_spi_mem_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!lvl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel(HC_EN_BIT, mxic->regs + HC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mxic->regs + HC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writel(0, mxic->regs + HC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int mxic_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct mxic_spi *mxic = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int busw = OP_BUSW_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (t->rx_buf && t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (((spi->mode & SPI_TX_QUAD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) !(spi->mode & SPI_RX_QUAD)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ((spi->mode & SPI_TX_DUAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) !(spi->mode & SPI_RX_DUAL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = mxic_spi_set_freq(mxic, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (spi->mode & SPI_TX_QUAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) busw = OP_BUSW_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else if (spi->mode & SPI_TX_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) busw = OP_BUSW_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (spi->mode & SPI_RX_QUAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) busw = OP_BUSW_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else if (spi->mode & SPI_RX_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) busw = OP_BUSW_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mxic->regs + SS_CTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct mxic_spi *mxic = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mxic_spi_clk_disable(mxic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_disable_unprepare(mxic->ps_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct mxic_spi *mxic = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = clk_prepare_enable(mxic->ps_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(dev, "Cannot enable ps_clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return mxic_spi_clk_enable(mxic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mxic_spi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int mxic_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct mxic_spi *mxic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mxic = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (IS_ERR(mxic->ps_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return PTR_ERR(mxic->ps_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (IS_ERR(mxic->send_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return PTR_ERR(mxic->send_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (IS_ERR(mxic->send_dly_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return PTR_ERR(mxic->send_dly_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mxic->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (IS_ERR(mxic->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return PTR_ERR(mxic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) master->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) master->mem_ops = &mxic_spi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) master->set_cs = mxic_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) master->transfer_one = mxic_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) master->mode_bits = SPI_CPOL | SPI_CPHA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SPI_RX_DUAL | SPI_TX_DUAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SPI_RX_QUAD | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mxic_spi_hw_init(mxic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(&pdev->dev, "spi_register_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int mxic_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct of_device_id mxic_spi_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { .compatible = "mxicy,mx25f0a-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct platform_driver mxic_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .probe = mxic_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .remove = mxic_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "mxic-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .of_match_table = mxic_spi_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .pm = &mxic_spi_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) module_platform_driver(mxic_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_DESCRIPTION("MX25F0A SPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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