Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // Some parts are based on spi-orion.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //   Author: Shadi Ammouri <shadi@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) //   Copyright (C) 2007-2008 Marvell Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DRIVER_NAME		"spi-mt7621"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* in usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RALINK_SPI_WAIT_MAX_LOOP 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* SPISTAT register bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SPISTAT_BUSY		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MT7621_SPI_TRANS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPITRANS_BUSY		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MT7621_SPI_OPCODE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MT7621_SPI_DATA0	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MT7621_SPI_DATA4	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SPI_CTL_TX_RX_CNT_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SPI_CTL_START		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MT7621_SPI_MASTER	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MASTER_MORE_BUFMODE	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MASTER_FULL_DUPLEX	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MASTER_RS_CLK_SEL	GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MASTER_RS_CLK_SEL_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MT7621_SPI_MOREBUF	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MT7621_SPI_POLAR	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MT7621_SPI_SPACE	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MT7621_CPHA		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MT7621_CPOL		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MT7621_LSB_FIRST	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct mt7621_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct spi_controller	*master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int		sys_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int		speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int			pending_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return spi_controller_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return ioread32(rs->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	iowrite32(val, rs->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 polar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * Select SPI device 7, enable "more buffer mode" and disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * full-duplex (only half-duplex really works on this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * reliably)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	master &= ~MASTER_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	rs->pending_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		polar = BIT(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	dev_dbg(&spi->dev, "speed:%u\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	rate = DIV_ROUND_UP(rs->sys_freq, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (rate > 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (rate < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		rate = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	reg &= ~MASTER_RS_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	rs->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	reg &= ~MT7621_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		reg |= MT7621_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * This SPI controller seems to be tested on SPI flash only and some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * bits are swizzled under other SPI modes probably due to incorrect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * wiring inside the silicon. Only mode 0 works correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	reg &= ~(MT7621_CPHA | MT7621_CPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if ((status & SPITRANS_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					int rx_len, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * Combine with any pending write, and perform one or more half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * transactions reading 'len' bytes. Data to be written is already in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * MT7621_SPI_DATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tx_len = rs->pending_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rs->pending_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	while (rx_len || tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		u32 val = (min(tx_len, 4) * 8) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		int rx = min(rx_len, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (tx_len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			val |= (tx_len - 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		val |= (rx * 8) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		val |= SPI_CTL_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		mt7621_spi_wait_till_ready(rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		for (i = 0; i < rx; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			if ((i % 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			*buf++ = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		rx_len -= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void mt7621_spi_flush(struct mt7621_spi *rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mt7621_spi_read_half_duplex(rs, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					 int tx_len, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int len = rs->pending_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (len & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		if (len < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			val <<= (4 - len) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			val = swab32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	while (tx_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (len >= 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			rs->pending_write = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			mt7621_spi_flush(rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		val |= *buf++ << (8 * (len & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if ((len & 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			if (len == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				/* The byte-order of the opcode is weird! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				val = swab32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		tx_len -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (len & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (len < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			val = swab32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			val >>= (4 - len) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	rs->pending_write = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int mt7621_spi_transfer_one_message(struct spi_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					   struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct mt7621_spi *rs = spi_controller_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned int speed = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct spi_transfer *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mt7621_spi_wait_till_ready(rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	list_for_each_entry(t, &m->transfers, transfer_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (t->speed_hz < speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			speed = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (mt7621_spi_prepare(spi, speed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		goto msg_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Assert CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	mt7621_spi_set_cs(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	m->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		if ((t->rx_buf) && (t->tx_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			 * This controller will shift some extra data out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			 * of spi_opcode if (mosi_bit_cnt > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			 * (cmd_bit_cnt == 0). So the claimed full-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			 * support is broken since we have no way to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			 * the MISO value during that bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			goto msg_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		} else if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		} else if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Flush data and deassert CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mt7621_spi_flush(rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mt7621_spi_set_cs(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) msg_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mt7621_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if ((spi->max_speed_hz == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	    (spi->max_speed_hz > (rs->sys_freq / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		spi->max_speed_hz = rs->sys_freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct of_device_id mt7621_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ .compatible = "ralink,mt7621-spi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DEVICE_TABLE(of, mt7621_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int mt7621_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct spi_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct mt7621_spi *rs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	match = of_match_device(mt7621_spi_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	status = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		dev_info(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	master->mode_bits = SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	master->setup = mt7621_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	master->transfer_one_message = mt7621_spi_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	master->num_chipselect = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	dev_set_drvdata(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	rs = spi_controller_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	rs->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	rs->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	rs->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	rs->sys_freq = clk_get_rate(rs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	rs->pending_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ret = device_reset(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		dev_err(&pdev->dev, "SPI reset failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ret = spi_register_controller(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int mt7621_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct spi_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct mt7621_spi *rs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	master = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	rs = spi_controller_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	spi_unregister_controller(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	clk_disable_unprepare(rs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct platform_driver mt7621_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.of_match_table = mt7621_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.probe = mt7621_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.remove = mt7621_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) module_platform_driver(mt7621_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_DESCRIPTION("MT7621 SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_LICENSE("GPL");