^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC52xx SPI bus driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Secret Lab Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This is the driver for the MPC5200's dedicated SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Note: this driver does not support the MPC5200 PSC in SPI mode. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * that driver see drivers/spi/mpc52xx_psc_spi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_CTRL1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_CTRL1_SPIE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_CTRL1_SPE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_CTRL1_MSTR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_CTRL1_CPOL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_CTRL1_CPHA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_CTRL1_SSOE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_CTRL1_LSBFE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_CTRL2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPI_BRR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_STATUS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPI_STATUS_SPIF (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_STATUS_WCOL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_STATUS_MODF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_DATA 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_PORTDATA 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_DATADIR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* FSM state return values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSM_STOP 0 /* Nothing more for the state machine to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* do. If something interesting happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* then an IRQ will be received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSM_POLL 1 /* need to poll for completion, an IRQ is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* not expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSM_CONTINUE 2 /* Keep iterating the state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Driver internal data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct mpc52xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int irq0; /* MODF irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq1; /* SPIF irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int ipb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Statistics; not used now, but will be reintroduced for debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int msg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int wcol_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int wcol_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 wcol_tx_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int modf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct list_head queue; /* queue of pending messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Details of current transfer (length, and buffer pointers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct spi_message *message; /* current message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spi_transfer *transfer; /* current transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int gpio_cs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int *gpio_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * CS control function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ms->gpio_cs_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cs = ms->message->spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Start a new transfer. This is called both by the idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * for the first transfer in a message, and by the wait state when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * previous transfer in a message is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ms->rx_buf = ms->transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ms->tx_buf = ms->transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ms->len = ms->transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Activate the chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ms->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mpc52xx_spi_chipsel(ms, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ms->cs_change = ms->transfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Write out the first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ms->wcol_tx_timestamp = get_tbl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ms->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) out_8(ms->regs + SPI_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Forward declaration of state handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 status, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 status, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * IDLE state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * No transfers are in progress; if another transfer is pending then retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * it and kick it off. Otherwise, stop processing the state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int spr, sppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (status && (irq != NO_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Check if there is another transfer waiting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (list_empty(&ms->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return FSM_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* get the head of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) list_del_init(&ms->message->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Setup the controller parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spi = ms->message->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ctrl1 |= SPI_CTRL1_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ctrl1 |= SPI_CTRL1_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ctrl1 |= SPI_CTRL1_LSBFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) out_8(ms->regs + SPI_CTRL1, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Setup the controller speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* minimum divider is '2'. Also, add '1' to force rounding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * divider up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (sppr < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sppr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while (((sppr - 1) & ~0x7) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sppr--; /* sppr quantity in register is offset by 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (spr > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Don't overrun limits of SPI baudrate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spr = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sppr = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ms->cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ms->transfer = container_of(ms->message->transfers.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mpc52xx_spi_start_transfer(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ms->state = mpc52xx_spi_fsmstate_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * TRANSFER state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * In the middle of a transfer. If the SPI core has completed processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * a byte, then read out the received data and write out the next byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * (unless this transfer is finished; in which case go on to the wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 status, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ms->irq0 ? FSM_STOP : FSM_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (status & SPI_STATUS_WCOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* The SPI controller is stoopid. At slower speeds, it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * raise the SPIF flag before the state machine is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * finished, which causes a collision (internal to the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * machine only). The manual recommends inserting a delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * between receiving the interrupt and sending the next byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * but it can also be worked around simply by retrying the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * transfer which is what we do here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ms->wcol_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ms->wcol_tx_timestamp = get_tbl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ms->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) data = *(ms->tx_buf - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) out_8(ms->regs + SPI_DATA, data); /* try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else if (status & SPI_STATUS_MODF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ms->modf_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(&ms->master->dev, "mode fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mpc52xx_spi_chipsel(ms, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ms->message->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ms->message->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ms->message->complete(ms->message->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ms->state = mpc52xx_spi_fsmstate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Read data out of the spi device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ms->byte_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ms->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *ms->rx_buf++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Is the transfer complete? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ms->len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ms->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ms->timestamp = get_tbl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ms->state = mpc52xx_spi_fsmstate_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Write out the next byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ms->wcol_tx_timestamp = get_tbl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ms->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) out_8(ms->regs + SPI_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * WAIT state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * A transfer has completed; need to wait for the delay period to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * before starting the next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (status && irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (((int)get_tbl()) - ms->timestamp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return FSM_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ms->message->actual_length += ms->transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Check if there is another transfer in this message. If there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * aren't then deactivate CS, notify sender, and drop back to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * to start the next message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ms->transfer->transfer_list.next == &ms->message->transfers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ms->msg_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mpc52xx_spi_chipsel(ms, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ms->message->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ms->message->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ms->message->complete(ms->message->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ms->state = mpc52xx_spi_fsmstate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* There is another transfer; kick it off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ms->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mpc52xx_spi_chipsel(ms, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ms->transfer = container_of(ms->transfer->transfer_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mpc52xx_spi_start_transfer(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ms->state = mpc52xx_spi_fsmstate_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * mpc52xx_spi_fsm_process - Finite State Machine iteration function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @irq: irq number that triggered the FSM or 0 for polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @ms: pointer to mpc52xx_spi driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int rc = FSM_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 status, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) while (rc == FSM_CONTINUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Interrupt cleared by read of STATUS followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * read of DATA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) status = in_8(ms->regs + SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) data = in_8(ms->regs + SPI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rc = ms->state(irq, ms, status, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (rc == FSM_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) schedule_work(&ms->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * mpc52xx_spi_irq - IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mpc52xx_spi *ms = _ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_lock(&ms->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mpc52xx_spi_fsm_process(irq, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spin_unlock(&ms->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * mpc52xx_spi_wq - Workqueue function for polling the state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void mpc52xx_spi_wq(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_lock_irqsave(&ms->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mpc52xx_spi_fsm_process(0, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) spin_unlock_irqrestore(&ms->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * spi_master ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) m->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) m->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irqsave(&ms->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) list_add_tail(&m->queue, &ms->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_unlock_irqrestore(&ms->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) schedule_work(&ms->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * OF Platform Bus Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int mpc52xx_spi_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct mpc52xx_spi *ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int rc, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int gpio_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* MMIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) regs = of_iomap(op->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* initialize the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) out_8(regs + SPI_CTRL1, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out_8(regs + SPI_CTRL2, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Clear the status register and re-read it to check for a MODF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * failure. This driver cannot currently handle multiple masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * on the SPI bus. This fault will also occur if the SPI signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * are not connected to any pins (port_config setting) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) in_8(regs + SPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) out_8(regs + SPI_CTRL1, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) in_8(regs + SPI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(&op->dev, "mode fault; is port_config correct?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_dbg(&op->dev, "allocating spi_master struct\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) master = spi_alloc_master(&op->dev, sizeof *ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) master->transfer = mpc52xx_spi_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) master->dev.of_node = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) platform_set_drvdata(op, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ms = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ms->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ms->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ms->state = mpc52xx_spi_fsmstate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ms->gpio_cs_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) master->num_chipselect = ms->gpio_cs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sizeof(*ms->gpio_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!ms->gpio_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto err_alloc_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) for (i = 0; i < ms->gpio_cs_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) gpio_cs = of_get_gpio(op->dev.of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!gpio_is_valid(gpio_cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(&op->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "could not parse the gpio field in oftree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rc = gpio_request(gpio_cs, dev_name(&op->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(&op->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "can't request spi cs gpio #%d on gpio line %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i, gpio_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpio_direction_output(gpio_cs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ms->gpio_cs[i] = gpio_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_lock_init(&ms->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) INIT_LIST_HEAD(&ms->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) INIT_WORK(&ms->work, mpc52xx_spi_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Decide if interrupts can be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ms->irq0 && ms->irq1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "mpc5200-spi-modf", ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "mpc5200-spi-spif", ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) free_irq(ms->irq0, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) free_irq(ms->irq1, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ms->irq0 = ms->irq1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* operate in polled mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ms->irq0 = ms->irq1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!ms->irq0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_info(&op->dev, "using polled mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_dbg(&op->dev, "registering spi_master struct\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rc = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(&ms->master->dev, "initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) err_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) while (i-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) gpio_free(ms->gpio_cs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) kfree(ms->gpio_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err_alloc_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int mpc52xx_spi_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct spi_master *master = spi_master_get(platform_get_drvdata(op));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct mpc52xx_spi *ms = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) free_irq(ms->irq0, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) free_irq(ms->irq1, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (i = 0; i < ms->gpio_cs_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) gpio_free(ms->gpio_cs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) kfree(ms->gpio_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) iounmap(ms->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct of_device_id mpc52xx_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .compatible = "fsl,mpc5200-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct platform_driver mpc52xx_spi_of_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .name = "mpc52xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .of_match_table = mpc52xx_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .probe = mpc52xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .remove = mpc52xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) module_platform_driver(mpc52xx_spi_of_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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