^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC52xx PSC in SPI mode driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Dragos Carp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 TOPTICA Photonics AG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mpc52xx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCLK 20000000 /* PSC port MClk in hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mpc52xx_psc_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* fsl_spi_platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void (*cs_control)(struct spi_device *spi, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* driver internal data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mpc52xx_psc __iomem *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mpc52xx_psc_fifo __iomem *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* controller state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mpc52xx_psc_spi_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* set clock freq, clock ramp, bits per work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * if t is NULL then reset the values to the default values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cs->speed_hz = (t && t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ? t->speed_hz : spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cs->bits_per_word = (t && t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ? t->bits_per_word : spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mpc52xx_psc __iomem *psc = mps->psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 sicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) sicr = in_be32(&psc->sicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Set clock phase and polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) sicr |= 0x00001000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) sicr &= ~0x00001000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sicr |= 0x00002000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) sicr &= ~0x00002000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sicr |= 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sicr &= ~0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) out_be32(&psc->sicr, sicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Set clock frequency and bits per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Because psc->ccr is defined as 16bit register instead of 32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * just set the lower byte of BitClkDiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ccr = in_be16((u16 __iomem *)&psc->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ccr &= 0xFF00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (cs->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else /* by default SPI Clk 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ccr |= (MCLK / 1000000 - 1) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) out_be16((u16 __iomem *)&psc->ccr, ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mps->bits_per_word = cs->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (mps->cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (mps->cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* wake up when 80% fifo full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mpc52xx_psc __iomem *psc = mps->psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned rb = 0; /* number of bytes receieved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned sb = 0; /* number of bytes sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char *rx_buf = (unsigned char *)t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char *tx_buf = (unsigned char *)t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned rfalarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned recv_at_once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int last_block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!t->tx_buf && !t->rx_buf && t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* enable transmiter/receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) while (rb < t->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rfalarm = MPC52xx_PSC_RFALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) last_block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) send_at_once = t->len - sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) last_block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (; send_at_once; sb++, send_at_once--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* set EOF flag before the last word is sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (send_at_once == 1 && last_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out_8(&psc->ircr2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) out_8(&psc->mpc52xx_psc_buffer_8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* enable interrupts and wait for wake up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * if just one byte is expected the Rx FIFO genererates no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * FFULL interrupt, so activate the RxRDY interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (t->len - rb == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) out_8(&psc->mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out_be16(&fifo->rfalarm, rfalarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wait_for_completion(&mps->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) recv_at_once = in_be16(&fifo->rfnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) send_at_once = recv_at_once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (; recv_at_once; rb++, recv_at_once--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (; recv_at_once; rb++, recv_at_once--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) in_8(&psc->mpc52xx_psc_buffer_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* disable transmiter/receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void mpc52xx_psc_spi_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mpc52xx_psc_spi *mps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) container_of(work, struct mpc52xx_psc_spi, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_lock_irq(&mps->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mps->busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) while (!list_empty(&mps->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct spi_message *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct spi_transfer *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) m = container_of(mps->queue.next, struct spi_message, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) list_del_init(&m->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock_irq(&mps->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) list_for_each_entry (t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (t->bits_per_word || t->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) status = mpc52xx_psc_spi_transfer_setup(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mpc52xx_psc_spi_activate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mpc52xx_psc_spi_deactivate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (m->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) m->complete(m->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (status || !cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mpc52xx_psc_spi_deactivate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mpc52xx_psc_spi_transfer_setup(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spin_lock_irq(&mps->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mps->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_unlock_irq(&mps->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int mpc52xx_psc_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (spi->bits_per_word%8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cs = kzalloc(sizeof *cs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cs->bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cs->speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock_irqsave(&mps->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!mps->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mpc52xx_psc_spi_deactivate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_unlock_irqrestore(&mps->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) m->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) m->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_lock_irqsave(&mps->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) list_add_tail(&m->queue, &mps->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) schedule_work(&mps->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock_irqrestore(&mps->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) kfree(spi->controller_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mpc52xx_psc __iomem *psc = mps->psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 mclken_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* default sysclk is 512MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Reset the PSC into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) out_8(&psc->command, MPC52xx_PSC_RST_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) out_8(&psc->command, MPC52xx_PSC_RST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Disable interrupts, interrupts are based on alarm level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) out_be16(&psc->mpc52xx_psc_imr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) out_8(&fifo->rfcntl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Configure 8bit codec mode as a SPI master and use EOF flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) out_be32(&psc->sicr, 0x0180C800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Set 2ms DTL delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) out_8(&psc->ctur, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) out_8(&psc->ctlr, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mps->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct mpc52xx_psc __iomem *psc = mps->psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* disable interrupt and wake up the work queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) out_be16(&psc->mpc52xx_psc_imr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) complete(&mps->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* bus_num is used only for the case dev->platform_data == NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 size, unsigned int irq, s16 bus_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mpc52xx_psc_spi *mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) master = spi_alloc_master(dev, sizeof *mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (master == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_set_drvdata(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mps->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "probe called without platform data, no cs_control function will be called\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mps->cs_control = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mps->sysclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) master->bus_num = bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) master->num_chipselect = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mps->cs_control = pdata->cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mps->sysclk = pdata->sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) master->bus_num = pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) master->num_chipselect = pdata->max_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) master->setup = mpc52xx_psc_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) master->transfer = mpc52xx_psc_spi_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) master->cleanup = mpc52xx_psc_spi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mps->psc = ioremap(regaddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!mps->psc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(dev, "could not ioremap I/O port range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* On the 5200, fifo regs are immediately ajacent to the psc regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_lock_init(&mps->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) init_completion(&mps->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) INIT_LIST_HEAD(&mps->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) free_irq(mps->irq, mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (mps->psc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) iounmap(mps->psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const u32 *regaddr_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u64 regaddr64, size64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s16 id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!regaddr_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&op->dev, "Invalid PSC address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* get PSC id (1..6, used by port_config) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (op->dev.platform_data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const u32 *psc_nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!psc_nump || *psc_nump > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(&op->dev, "Invalid cell-index property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) id = *psc_nump + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) irq_of_parse_and_map(op->dev.of_node, 0), id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct spi_master *master = spi_master_get(platform_get_drvdata(op));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) flush_work(&mps->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) free_irq(mps->irq, mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (mps->psc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iounmap(mps->psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { .compatible = "fsl,mpc5200-psc-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { .compatible = "mpc5200-psc-spi", }, /* old */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct platform_driver mpc52xx_psc_spi_of_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .probe = mpc52xx_psc_spi_of_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .remove = mpc52xx_psc_spi_of_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .name = "mpc52xx-psc-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .of_match_table = mpc52xx_psc_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) module_platform_driver(mpc52xx_psc_spi_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MODULE_AUTHOR("Dragos Carp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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