^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC512x PSC in SPI mode driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Original port from 52xx driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Hongjun Chen <hong-jun.chen@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Fork of mpc52xx_psc_spi.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mpc52xx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TYPE_MPC5121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) TYPE_MPC5125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * This macro abstracts the differences in the PSC register layout between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define psc_addr(mps, regname) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void *__ret = NULL; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) switch (mps->type) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case TYPE_MPC5121: { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mpc52xx_psc __iomem *psc = mps->psc; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __ret = &psc->regname; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case TYPE_MPC5125: { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mpc5125_psc __iomem *psc = mps->psc; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __ret = &psc->regname; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __ret; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct mpc512x_psc_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void (*cs_control)(struct spi_device *spi, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* driver internal data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct mpc512x_psc_fifo __iomem *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk *clk_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct completion txisrdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* controller state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mpc512x_psc_spi_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* set clock freq, clock ramp, bits per work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * if t is NULL then reset the values to the default values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mpc512x_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) cs->speed_hz = (t && t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ? t->speed_hz : spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cs->bits_per_word = (t && t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ? t->bits_per_word : spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mpc512x_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 sicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 bclkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sicr = in_be32(psc_addr(mps, sicr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Set clock phase and polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sicr |= 0x00001000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sicr &= ~0x00001000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sicr |= 0x00002000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sicr &= ~0x00002000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sicr |= 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sicr &= ~0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) out_be32(psc_addr(mps, sicr), sicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ccr = in_be32(psc_addr(mps, ccr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ccr &= 0xFF000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) speed = cs->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) speed = 1000000; /* default 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bclkdiv = (mps->mclk_rate / speed) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) out_be32(psc_addr(mps, ccr), ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mps->bits_per_word = cs->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* extract and scale size field in txsz or rxsz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EOFBYTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) size_t tx_len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) size_t rx_len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 *tx_buf = (u8 *)t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 *rx_buf = (u8 *)t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!tx_buf && !rx_buf && t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) while (rx_len || tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) size_t txcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) size_t fifosz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) size_t rxcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int rxtries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * send the TX bytes in as large a chunk as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * but neither exceed the TX nor the RX FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) txcount = min(fifosz, tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fifosz -= in_be32(&fifo->rxcnt) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) txcount = min(fifosz, txcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (txcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* fill the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (txcount-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) data = tx_buf ? *tx_buf++ : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (tx_len == EOFBYTE && t->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) setbits32(&fifo->txcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MPC512x_PSC_FIFO_EOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) out_8(&fifo->txdata_8, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tx_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* have the ISR trigger when the TX FIFO is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reinit_completion(&mps->txisrdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) wait_for_completion(&mps->txisrdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * consume as much RX data as the FIFO holds, while we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * iterate over the transfer's TX data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * only insist in draining all the remaining RX bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * when the TX bytes were exhausted (that's at the very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * end of this transfer, not when still iterating over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * the transfer's chunks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rxtries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * grab whatever was in the FIFO when we started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * looking, don't bother fetching what was added to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * the FIFO while we read from it -- we'll return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * here eventually and prefer sending out remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * TX data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) fifosz = in_be32(&fifo->rxcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rxcount = min(fifosz, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) while (rxcount-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data = in_8(&fifo->rxdata_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *rx_buf++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rx_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * come back later if there still is TX data to send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * bail out of the RX drain loop if all of the TX data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * was sent and all of the RX data was received (i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * when the transmission has completed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!rx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * TX data transmission has completed while RX data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * is still pending -- that's a transient situation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * which depends on wire speed and specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * hardware implementation details (buffering) yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * should resolve very quickly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * just yield for a moment to not hog the CPU for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * too long when running SPI at low speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * the timeout range is rather arbitrary and tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * to balance throughput against system load; the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * chosen values result in a minimal timeout of 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * times 10us and thus work at speeds as low as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * some 20kbps, while the maximum timeout at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * transfer's end could be 5ms _if_ nothing else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * ticks in the system _and_ RX data still wasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * received, which only occurs in situations that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * are exceptional; removing the unpredictability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * of the timeout either decreases throughput
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * (longer timeouts), or puts more load on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * system (fixed short timeouts) or requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * use of a timeout API instead of a counter and an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * unknown inner delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } while (--rxtries > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!tx_len && rx_len && !rxtries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * not enough RX bytes even after several retries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * and the resulting rather long timeout?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rxcount = in_be32(&fifo->rxcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "short xfer, missing %zd RX bytes, FIFO level %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rx_len, rxcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * drain and drop RX data which "should not be there" in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * the first place, for undisturbed transmission this turns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * into a NOP (except for the FIFO level fetch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!tx_len && !rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) while (in_be32(&fifo->rxcnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) in_8(&fifo->rxdata_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) status = mpc512x_psc_spi_transfer_setup(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mpc512x_psc_spi_activate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) status = mpc512x_psc_spi_transfer_rxtx(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mpc512x_psc_spi_deactivate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (m->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) m->complete(m->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (status || !cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mpc512x_psc_spi_deactivate_cs(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mpc512x_psc_spi_transfer_setup(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(&master->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Zero MR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) in_8(psc_addr(mps, mr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) out_8(psc_addr(mps, mr2), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* enable transmitter/receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_dbg(&master->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* disable transmitter/receiver and fifo interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) out_be32(&fifo->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int mpc512x_psc_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct mpc512x_psc_spi_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (spi->bits_per_word % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cs = kzalloc(sizeof *cs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (gpio_is_valid(spi->cs_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(&spi->dev, "can't get CS gpio: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) gpio_direction_output(spi->cs_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spi->mode & SPI_CS_HIGH ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cs->bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cs->speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (gpio_is_valid(spi->cs_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) gpio_free(spi->cs_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) kfree(spi->controller_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int mpc512x_psc_spi_port_config(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mpc512x_psc_spi *mps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 sicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u16 bclkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Reset the PSC into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Disable psc interrupts all useful interrupts are in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) out_be16(psc_addr(mps, isr_imr.imr), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Disable fifo interrupts, will be enabled later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) out_be32(&fifo->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) out_be32(&fifo->rximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Setup fifo slice address and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*out_be32(&fifo->txsz, 0x0fe00004);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*out_be32(&fifo->rxsz, 0x0ff00004);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x00800000 | /* GenClk = 1 -- internal clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x00008000 | /* SPI = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x00004000 | /* MSTR = 1 -- SPI master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x00000800; /* UseEOF = 1 -- SS low until EOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) out_be32(psc_addr(mps, sicr), sicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ccr = in_be32(psc_addr(mps, ccr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ccr &= 0xFF000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) speed = 1000000; /* default 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bclkdiv = (mps->mclk_rate / speed) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) out_be32(psc_addr(mps, ccr), ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Set 2ms DTL delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) out_8(psc_addr(mps, ctur), 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) out_8(psc_addr(mps, ctlr), 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* we don't use the alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) out_be32(&fifo->rxalarm, 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) out_be32(&fifo->txalarm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Enable FIFO slices for Rx/Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) out_be32(&fifo->rxcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) out_be32(&fifo->txcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mps->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* clear interrupt and wake up the rx/tx routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (in_be32(&fifo->txisr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) out_be32(&fifo->tximr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) complete(&mps->txisrdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) gpio_set_value(spi->cs_gpio, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 size, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mpc512x_psc_spi *mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void *tempp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) master = spi_alloc_master(dev, sizeof *mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (master == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_set_drvdata(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mps->type = (int)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mps->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mps->cs_control = mpc512x_spi_cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mps->cs_control = pdata->cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) master->bus_num = pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) master->num_chipselect = pdata->max_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) master->setup = mpc512x_psc_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) master->cleanup = mpc512x_psc_spi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tempp = devm_ioremap(dev, regaddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!tempp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(dev, "could not ioremap I/O port range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mps->psc = tempp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mps->fifo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "mpc512x-psc-spi", mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) init_completion(&mps->txisrdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clk = devm_clk_get(dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mps->clk_mclk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mps->mclk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clk = devm_clk_get(dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto free_mclk_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto free_mclk_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mps->clk_ipg = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = mpc512x_psc_spi_port_config(master, mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto free_ipg_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto free_ipg_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) free_ipg_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clk_disable_unprepare(mps->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) free_mclk_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clk_disable_unprepare(mps->clk_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int mpc512x_psc_spi_do_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_disable_unprepare(mps->clk_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_disable_unprepare(mps->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int mpc512x_psc_spi_of_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const u32 *regaddr_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u64 regaddr64, size64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!regaddr_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(&op->dev, "Invalid PSC address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) irq_of_parse_and_map(op->dev.of_node, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int mpc512x_psc_spi_of_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return mpc512x_psc_spi_do_remove(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct of_device_id mpc512x_psc_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct platform_driver mpc512x_psc_spi_of_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .probe = mpc512x_psc_spi_of_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .remove = mpc512x_psc_spi_of_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .name = "mpc512x-psc-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .of_match_table = mpc512x_psc_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) module_platform_driver(mpc512x_psc_spi_of_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MODULE_AUTHOR("John Rigby");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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