^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Driver for Amlogic Meson SPI flash controller (SPIFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_CTRL1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_CTRL2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_CLOCK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_USER 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_USER1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_USER2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_USER3 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_USER4 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_SLAVE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_SLAVE1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_SLAVE2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_SLAVE3 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_C0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_B8 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_MAX 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_USER BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTRL_ENABLE_AHB BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLOCK_SOURCE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLOCK_DIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLOCK_CNT_HIGH_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLOCK_CNT_LOW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USER_DIN_EN_MS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USER_CMP_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USER_UC_DOUT_SEL BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USER_UC_DIN_SEL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USER_UC_MASK ((BIT(5) - 1) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USER1_BN_UC_DOUT_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USER1_BN_UC_DOUT_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USER1_BN_UC_DIN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USER1_BN_UC_DIN_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USER4_CS_ACT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLAVE_TRST_DONE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLAVE_OP_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLAVE_SW_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPIFC_BUFFER_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * struct meson_spifc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @master: the SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @regmap: regmap for device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @clk: input clock of the built-in baud rate generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @dev: the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct meson_spifc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct regmap_config spifc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .max_register = REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * meson_spifc_wait_ready() - wait for the current operation to terminate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Return: 0 on success, a negative value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int meson_spifc_wait_ready(struct meson_spifc *spifc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long deadline = jiffies + msecs_to_jiffies(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_read(spifc->regmap, REG_SLAVE, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (data & SLAVE_TRST_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } while (!time_after(jiffies, deadline));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * meson_spifc_drain_buffer() - copy data from device buffer to memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @buf: the destination buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @len: number of bytes to copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) while (i < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_read(spifc->regmap, REG_C0 + i, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (len - i >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *((u32 *)buf) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) memcpy(buf, &data, len - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * meson_spifc_fill_buffer() - copy data from memory to device buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @buf: the source buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @len: number of bytes to copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) while (i < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (len - i >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) data = *(u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) memcpy(&data, buf, len - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_write(spifc->regmap, REG_C0 + i, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * meson_spifc_setup_speed() - program the clock divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @speed: desired speed in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long parent, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) parent = clk_get_rate(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) n = max_t(int, parent / speed - 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) speed, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLOCK_CNT_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_write(spifc->regmap, REG_CLOCK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * meson_spifc_txrx() - transfer a chunk of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @xfer: the current SPI transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @offset: offset of the data to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @len: length of the data to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @last_xfer: whether this is the last transfer of the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @last_chunk: whether this is the last chunk of the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Return: 0 on success, a negative value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int meson_spifc_txrx(struct meson_spifc *spifc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct spi_transfer *xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int offset, int len, bool last_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool last_chunk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool keep_cs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* enable DOUT stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) USER_UC_DOUT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regmap_write(spifc->regmap, REG_USER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* enable data input during DOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) USER_DIN_EN_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (last_chunk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (last_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) keep_cs = xfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) keep_cs = !xfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) keep_cs ? USER4_CS_ACT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* clear transition done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = meson_spifc_wait_ready(spifc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!ret && xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * meson_spifc_transfer_one() - perform a single transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @master: the SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @spi: the SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @xfer: the current SPI transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Return: 0 on success, a negative value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int meson_spifc_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int len, done = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) meson_spifc_setup_speed(spifc, xfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while (done < xfer->len && !ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = meson_spifc_txrx(spifc, xfer, done, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spi_transfer_is_last(master, xfer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) done + len >= xfer->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) done += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CTRL_ENABLE_AHB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * meson_spifc_hw_init() - reset and initialize the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @spifc: the Meson SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void meson_spifc_hw_init(struct meson_spifc *spifc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* reset device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SLAVE_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* disable compatible mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* set master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int meson_spifc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct meson_spifc *spifc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spifc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spifc->regmap = devm_regmap_init_mmio(spifc->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &spifc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(spifc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = PTR_ERR(spifc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spifc->clk = devm_clk_get(spifc->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR(spifc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(spifc->dev, "missing clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = PTR_ERR(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = clk_prepare_enable(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(spifc->dev, "can't prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rate = clk_get_rate(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) master->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) master->transfer_one = meson_spifc_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) master->min_speed_hz = rate >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) master->max_speed_hz = rate >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) meson_spifc_hw_init(spifc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pm_runtime_set_active(spifc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pm_runtime_enable(spifc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = devm_spi_register_master(spifc->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(spifc->dev, "failed to register spi master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_disable_unprepare(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pm_runtime_disable(spifc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int meson_spifc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clk_disable_unprepare(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int meson_spifc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clk_disable_unprepare(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int meson_spifc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!pm_runtime_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = clk_prepare_enable(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) meson_spifc_hw_init(spifc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_disable_unprepare(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int meson_spifc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_disable_unprepare(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int meson_spifc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct meson_spifc *spifc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return clk_prepare_enable(spifc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct dev_pm_ops meson_spifc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) meson_spifc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct of_device_id meson_spifc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { .compatible = "amlogic,meson6-spifc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { .compatible = "amlogic,meson-gxbb-spifc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(of, meson_spifc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct platform_driver meson_spifc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .probe = meson_spifc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .remove = meson_spifc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "meson-spifc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .of_match_table = of_match_ptr(meson_spifc_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .pm = &meson_spifc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) module_platform_driver(meson_spifc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DESCRIPTION("Amlogic Meson SPIFC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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