^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for Amlogic Meson SPI communication controller (SPICC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The Meson SPICC controller could support DMA based transfers, but is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * implemented by the vendor code, and while having the registers documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * it has never worked on the GXL Hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The PIO mode is the only mode implemented, and due to badly designed HW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - all transfers are cutted in 16 words burst because the FIFO hangs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * FIFO max size chunk only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - CS management is dumb, and goes UP between every burst, so is really a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * "Data Valid" signal than a Chip Select, GPIO link should be used instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * to have a CS go down over the full transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPICC_MAX_BURST 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPICC_RXDATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPICC_TXDATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPICC_CONREG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPICC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPICC_MODE_MASTER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPICC_XCH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPICC_SMC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPICC_POL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPICC_PHA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPICC_SSCTL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPICC_SSPOL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPICC_DRCTL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPICC_DRCTL_IGNORE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPICC_DRCTL_FALLING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPICC_DRCTL_LOWLEVEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPICC_CS_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPICC_DATARATE_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPICC_DATARATE_DIV4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPICC_DATARATE_DIV8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPICC_DATARATE_DIV16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPICC_DATARATE_DIV32 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPICC_BITLENGTH_MASK GENMASK(24, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPICC_INTREG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPICC_DMAREG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPICC_DMA_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPICC_READ_BURST_MASK GENMASK(14, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPICC_DMA_URGENT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPICC_STATREG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPICC_PERIODREG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPICC_TESTREG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPICC_MO_NO_DELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPICC_MO_DELAY_1_CYCLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPICC_MO_DELAY_2_CYCLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SPICC_MO_DELAY_3_CYCLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SPICC_MI_NO_DELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPICC_MI_DELAY_1_CYCLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPICC_MI_DELAY_2_CYCLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPICC_MI_DELAY_3_CYCLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPICC_CAP_AHEAD_2_CYCLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SPICC_CAP_AHEAD_1_CYCLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPICC_CAP_NO_DELAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SPICC_CAP_DELAY_1_CYCLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPICC_DRADDR 0x20 /* Read Address of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SPICC_DWADDR 0x24 /* Write Address of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SPICC_ENH_DATARATE_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SPICC_ENH_MOSI_OEN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SPICC_ENH_CLK_OEN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SPICC_ENH_CS_OEN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SPICC_ENH_MAIN_CLK_AO BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define writel_bits_relaxed(mask, val, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct meson_spicc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int min_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool has_oen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool has_enhance_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool has_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct meson_spicc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct spi_message *message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct spi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const struct meson_spicc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long tx_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long rx_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long xfer_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!spicc->data->has_oen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return !!FIELD_GET(SPICC_TF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) readl_relaxed(spicc->base + SPICC_STATREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) readl_relaxed(spicc->base + SPICC_STATREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int bytes = spicc->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int byte_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) byte = *spicc->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data |= (byte & 0xff) << byte_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) byte_shift += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spicc->tx_remain--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int bytes = spicc->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int byte_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) byte = (data >> byte_shift) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *spicc->rx_buf++ = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) byte_shift += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spicc->rx_remain--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Empty RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while (spicc->rx_remain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) meson_spicc_rxready(spicc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) meson_spicc_push_data(spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) readl_relaxed(spicc->base + SPICC_RXDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Fill Up TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) while (spicc->tx_remain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) !meson_spicc_txfull(spicc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel_relaxed(meson_spicc_pull_data(spicc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spicc->base + SPICC_TXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int burst_len = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spicc->xfer_remain /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spicc->bytes_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spicc->data->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Setup Xfer variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spicc->tx_remain = burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spicc->rx_remain = burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Setup burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FIELD_PREP(SPICC_BURSTLENGTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) burst_len - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Fill TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) meson_spicc_tx(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static irqreturn_t meson_spicc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct meson_spicc_device *spicc = (void *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Empty RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) meson_spicc_rx(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!spicc->xfer_remain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel(0, spicc->base + SPICC_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spi_finalize_current_transfer(spicc->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Setup burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) meson_spicc_setup_burst(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Start burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 div, hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 mi_delay, cap_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (spicc->data->has_enhance_clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) readl_relaxed(spicc->base + SPICC_ENH_CTL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) div <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) div = FIELD_GET(SPICC_DATARATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) readl_relaxed(spicc->base + SPICC_CONREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) div += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) div = 1 << div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mi_delay = SPICC_MI_NO_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) hz = clk_get_rate(spicc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (hz >= 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) cap_delay = SPICC_CAP_DELAY_1_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else if (hz >= 80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cap_delay = SPICC_CAP_NO_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else if (hz >= 40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (div >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mi_delay = SPICC_MI_DELAY_3_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else if (div >= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mi_delay = SPICC_MI_DELAY_2_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else if (div >= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mi_delay = SPICC_MI_DELAY_1_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) conf = readl_relaxed(spicc->base + SPICC_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) | SPICC_MI_CAP_DELAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel_relaxed(conf, spicc->base + SPICC_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 conf, conf_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Read original configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Setup word width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) conf &= ~SPICC_BITLENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (spicc->bytes_per_word << 3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Ignore if unchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (conf != conf_orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel_relaxed(conf, spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_set_rate(spicc->clk, xfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) meson_spicc_auto_io_delay(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel_relaxed(0, spicc->base + SPICC_DMAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (spicc->data->has_oen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SPICC_ENH_MAIN_CLK_AO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spicc->base + SPICC_ENH_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spicc->base + SPICC_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) while (meson_spicc_rxready(spicc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) readl_relaxed(spicc->base + SPICC_RXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (spicc->data->has_oen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spicc->base + SPICC_ENH_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int meson_spicc_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct meson_spicc_device *spicc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Store current transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spicc->xfer = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Setup transfer parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) spicc->tx_buf = (u8 *)xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spicc->rx_buf = (u8 *)xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spicc->xfer_remain = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Pre-calculate word size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spicc->bytes_per_word =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (xfer->len % spicc->bytes_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Setup transfer parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) meson_spicc_setup_xfer(spicc, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) meson_spicc_reset_fifo(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Setup burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) meson_spicc_setup_burst(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Start burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int meson_spicc_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct meson_spicc_device *spicc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct spi_device *spi = message->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Store current message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spicc->message = message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Enable Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) conf |= SPICC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) conf |= SPICC_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* SMC = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Setup transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) conf |= SPICC_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) conf &= ~SPICC_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) conf |= SPICC_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) conf &= ~SPICC_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* SSCTL = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) conf |= SPICC_SSPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) conf &= ~SPICC_SSPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (spi->mode & SPI_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Select CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Default Clock rate core/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Default 8bit word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writel_relaxed(conf, spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Setup no wait cycles by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writel_relaxed(0, spicc->base + SPICC_PERIODREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int meson_spicc_unprepare_transfer(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct meson_spicc_device *spicc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writel(0, spicc->base + SPICC_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) device_reset_optional(&spicc->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int meson_spicc_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!spi->controller_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) spi->controller_state = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void meson_spicc_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spi->controller_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * The Clock Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * x-----------------x x------------x x------\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * |---| pow2 fixed div |---| pow2 div |----| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * | x-----------------x x------------x | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * src ---| | mux |-- out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * | x-----------------x x------------x | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * |---| enh fixed div |---| enh div |0---| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * x-----------------x x------------x x------/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Clk path for GX series:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * src -> pow2 fixed div -> pow2 div -> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Clk path for AXG series:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * src -> pow2 fixed div -> pow2 div -> mux -> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * src -> enh fixed div -> enh div -> mux -> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Clk path for G12A series:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * pclk -> pow2 fixed div -> pow2 div -> mux -> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * pclk -> enh fixed div -> enh div -> mux -> out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct device *dev = &spicc->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct clk_divider *pow2_div, *enh_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct clk_parent_data parent_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) char name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) memset(&parent_data, 0, sizeof(parent_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) init.parent_data = parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pow2_fixed_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) init.ops = &clk_fixed_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (spicc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) parent_data[0].hw = __clk_get_hw(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) parent_data[0].hw = __clk_get_hw(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pow2_fixed_div->mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pow2_fixed_div->div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pow2_fixed_div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clk = devm_clk_register(dev, &pow2_fixed_div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!pow2_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) init.ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) parent_data[0].hw = &pow2_fixed_div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pow2_div->shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pow2_div->width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pow2_div->reg = spicc->base + SPICC_CONREG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pow2_div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk = devm_clk_register(dev, &pow2_div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!spicc->data->has_enhance_clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) spicc->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* algorithm for enh div: rate = freq / 2 / (N + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!enh_fixed_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) init.ops = &clk_fixed_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (spicc->data->has_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) parent_data[0].hw = __clk_get_hw(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) parent_data[0].hw = __clk_get_hw(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) enh_fixed_div->mult = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) enh_fixed_div->div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) enh_fixed_div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk = devm_clk_register(dev, &enh_fixed_div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!enh_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) init.ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) parent_data[0].hw = &enh_fixed_div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) enh_div->shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) enh_div->width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enh_div->reg = spicc->base + SPICC_ENH_CTL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) enh_div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clk = devm_clk_register(dev, &enh_div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) init.ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) parent_data[0].hw = &pow2_div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) parent_data[1].hw = &enh_div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mux->mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mux->shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mux->reg = spicc->base + SPICC_ENH_CTL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) spicc->clk = devm_clk_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (WARN_ON(IS_ERR(spicc->clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return PTR_ERR(spicc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int meson_spicc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct meson_spicc_device *spicc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(&pdev->dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spicc = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spicc->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) spicc->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!spicc->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(&pdev->dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) spicc->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) platform_set_drvdata(pdev, spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) spicc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (IS_ERR(spicc->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(&pdev->dev, "io resource mapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = PTR_ERR(spicc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Set master mode and enable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel_relaxed(0, spicc->base + SPICC_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0, NULL, spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(&pdev->dev, "irq request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) spicc->core = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (IS_ERR(spicc->core)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_err(&pdev->dev, "core clock request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = PTR_ERR(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (spicc->data->has_pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (IS_ERR(spicc->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(&pdev->dev, "pclk clock request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = PTR_ERR(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = clk_prepare_enable(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(&pdev->dev, "core clock enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto out_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = clk_prepare_enable(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_err(&pdev->dev, "pclk clock enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto out_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) device_reset_optional(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) master->bits_per_word_mask = SPI_BPW_MASK(32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SPI_BPW_MASK(24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SPI_BPW_MASK(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) master->min_speed_hz = spicc->data->min_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) master->max_speed_hz = spicc->data->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) master->setup = meson_spicc_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) master->cleanup = meson_spicc_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) master->prepare_message = meson_spicc_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) master->transfer_one = meson_spicc_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) meson_spicc_oen_enable(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = meson_spicc_clk_init(spicc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_err(&pdev->dev, "clock registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_err(&pdev->dev, "spi master registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) clk_disable_unprepare(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) out_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) clk_disable_unprepare(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) out_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int meson_spicc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Disable SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) writel(0, spicc->base + SPICC_CONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) clk_disable_unprepare(spicc->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) clk_disable_unprepare(spicc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) spi_master_put(spicc->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct meson_spicc_data meson_spicc_gx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .max_speed_hz = 30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .min_speed_hz = 325000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const struct meson_spicc_data meson_spicc_axg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .max_speed_hz = 80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .min_speed_hz = 325000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .has_oen = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .has_enhance_clk_div = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct meson_spicc_data meson_spicc_g12a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .max_speed_hz = 166666666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .min_speed_hz = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .fifo_size = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .has_oen = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .has_enhance_clk_div = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .has_pclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const struct of_device_id meson_spicc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .compatible = "amlogic,meson-gx-spicc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .data = &meson_spicc_gx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .compatible = "amlogic,meson-axg-spicc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .data = &meson_spicc_axg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .compatible = "amlogic,meson-g12a-spicc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .data = &meson_spicc_g12a_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct platform_driver meson_spicc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .probe = meson_spicc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .remove = meson_spicc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "meson-spicc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .of_match_table = of_match_ptr(meson_spicc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) module_platform_driver(meson_spicc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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