^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for LM70EVAL-LLP board for the LM70 sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Kaiwan N Billimoria <kaiwan@designergraphix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/parport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The LM70 communicates with a host processor using a 3-wire variant of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * the SPI/Microwire bus interface. This driver specifically supports an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * NS LM70 LLP Evaluation Board, interfacing to a PC using its parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * port to bitbang an SPI-parport bridge. Accordingly, this is an SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * master controller driver. The hwmon/lm70 driver is a "SPI protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * driver", layered on top of this one and usable without the lm70llp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Datasheet and Schematic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The LM70 is a temperature sensor chip from National Semiconductor; its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * datasheet is available at http://www.national.com/pf/LM/LM70.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The schematic for this particular board (the LM70EVAL-LLP) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * available (on page 4) here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Also see Documentation/spi/spi-lm70llp.rst. The SPI<->parport code here is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * (heavily) based on spi-butterfly by David Brownell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The LM70 LLP connects to the PC parallel port in the following manner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Parallel LM70 LLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Port Direction JP2 Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ----------- --------- ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * D0 2 - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * D1 3 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * D2 4 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * D3 5 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * D4 6 --> V+ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * D5 7 --> nCS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * D6 8 --> SCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * D7 9 --> SI/O 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * GND 25 - GND 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Select 13 <-- SI/O 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Note that parport pin 13 actually gets inverted by the transistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * arrangement which lets either the parport or the LM70 drive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * SI/SO signal (see the schematic for details).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRVNAME "spi-lm70llp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define lm70_INIT 0xBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SIO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define nCS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCLK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct spi_lm70llp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct parport *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pardevice *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct spi_device *spidev_lm70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct spi_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) //struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* REVISIT : ugly global ; provides "exclusive open" facility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct spi_lm70llp *lm70llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*-------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline struct spi_lm70llp *spidev_to_pp(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*---------------------- LM70 LLP eval board-specific inlines follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* NOTE: we don't actually need to reread the output values, since they'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * still be what we wrote before. Plus, going through parport builds in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * a ~1ms/operation delay; these SPI transfers could easily be faster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void deassertCS(struct spi_lm70llp *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 data = parport_read_data(pp->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data &= ~0x80; /* pull D7/SI-out low while de-asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) parport_write_data(pp->port, data | nCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void assertCS(struct spi_lm70llp *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 data = parport_read_data(pp->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data |= 0x80; /* pull D7/SI-out high so lm70 drives SO-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) parport_write_data(pp->port, data & ~nCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void clkHigh(struct spi_lm70llp *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 data = parport_read_data(pp->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) parport_write_data(pp->port, data | SCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void clkLow(struct spi_lm70llp *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 data = parport_read_data(pp->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) parport_write_data(pp->port, data & ~SCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*------------------------- SPI-LM70-specific inlines ----------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void spidelay(unsigned d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) udelay(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline void setsck(struct spi_device *s, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct spi_lm70llp *pp = spidev_to_pp(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clkHigh(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clkLow(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void setmosi(struct spi_device *s, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* FIXME update D7 ... this way we can put the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * into shutdown mode and read the manufacturer ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * but we can't put it back into operational mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * getmiso:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Why do we return 0 when the SIO line is high and vice-versa?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * The fact is, the lm70 eval board from NS (which this driver drives),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * is wired in just such a way : when the lm70's SIO goes high, a transistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * switches it to low reflecting this on the parport (pin 13), and vice-versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline int getmiso(struct spi_device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct spi_lm70llp *pp = spidev_to_pp(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ((SIO == (parport_read_status(pp->port) & SIO)) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*--------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #include "spi-bitbang-txrx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void lm70_chipselect(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct spi_lm70llp *pp = spidev_to_pp(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) assertCS(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) deassertCS(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Our actual bitbanger routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 lm70_txrx(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void spi_lm70llp_attach(struct parport *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pardevice *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct spi_lm70llp *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pardev_cb lm70llp_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (lm70llp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_warn("spi_lm70llp instance already loaded. Aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* TODO: this just _assumes_ a lm70 is there ... no probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * the lm70 driver could verify it, reading the manf ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) master = spi_alloc_master(p->physport->dev, sizeof *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pp = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * SPI and bitbang hookup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pp->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pp->bitbang.chipselect = lm70_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pp->bitbang.txrx_word[SPI_MODE_0] = lm70_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pp->bitbang.flags = SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Parport hookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pp->port = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) memset(&lm70llp_cb, 0, sizeof(lm70llp_cb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lm70llp_cb.private = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) lm70llp_cb.flags = PARPORT_FLAG_EXCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pd = parport_register_dev_model(p, DRVNAME, &lm70llp_cb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto out_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pp->pd = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) status = parport_claim(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto out_parport_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Start SPI ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) status = spi_bitbang_start(&pp->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_warn(&pd->dev, "spi_bitbang_start failed with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto out_off_and_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * The modalias name MUST match the device_driver name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * for the bus glue code to match and subsequently bind them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * We are binding to the generic drivers/hwmon/lm70.c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) strcpy(pp->info.modalias, "lm70");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pp->info.max_speed_hz = 6 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pp->info.chip_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pp->info.mode = SPI_3WIRE | SPI_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* power up the chip, and let the LM70 control SI/SO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) parport_write_data(pp->port, lm70_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Enable access to our primary data structure via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * the board info's (void *)controller_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pp->info.controller_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pp->spidev_lm70 = spi_new_device(pp->bitbang.master, &pp->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (pp->spidev_lm70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_dbg(&pp->spidev_lm70->dev, "spidev_lm70 at %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_name(&pp->spidev_lm70->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_warn(&pd->dev, "spi_new_device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) status = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto out_bitbang_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pp->spidev_lm70->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) lm70llp = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out_bitbang_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spi_bitbang_stop(&pp->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) out_off_and_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) parport_write_data(pp->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) parport_release(pp->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out_parport_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) parport_unregister_device(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) out_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) out_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pr_info("spi_lm70llp probe fail, status %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void spi_lm70llp_detach(struct parport *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct spi_lm70llp *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!lm70llp || lm70llp->port != p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pp = lm70llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spi_bitbang_stop(&pp->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) parport_write_data(pp->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) parport_release(pp->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) parport_unregister_device(pp->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spi_master_put(pp->bitbang.master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) lm70llp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct parport_driver spi_lm70llp_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .match_port = spi_lm70llp_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .detach = spi_lm70llp_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .devmodel = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int __init init_spi_lm70llp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return parport_register_driver(&spi_lm70llp_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) module_init(init_spi_lm70llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void __exit cleanup_spi_lm70llp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) parport_unregister_driver(&spi_lm70llp_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) module_exit(cleanup_spi_lm70llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Kaiwan N Billimoria <kaiwan@designergraphix.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_DESCRIPTION(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "Parport adapter for the National Semiconductor LM70 LLP eval board");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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