^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_LANTIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LTQ_SPI_RX_IRQ_NAME "spi_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LTQ_SPI_TX_IRQ_NAME "spi_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LTQ_SPI_ERR_IRQ_NAME "spi_err"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LTQ_SPI_CLC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LTQ_SPI_PISEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LTQ_SPI_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LTQ_SPI_CON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LTQ_SPI_STAT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LTQ_SPI_WHBSTATE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LTQ_SPI_TB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LTQ_SPI_RB 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LTQ_SPI_RXFCON 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LTQ_SPI_TXFCON 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LTQ_SPI_FSTAT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LTQ_SPI_BRT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LTQ_SPI_BRSTAT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LTQ_SPI_SFCON 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LTQ_SPI_SFSTAT 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LTQ_SPI_GPOCON 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LTQ_SPI_GPOSTAT 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LTQ_SPI_FPGO 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LTQ_SPI_RXREQ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LTQ_SPI_RXCNT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LTQ_SPI_DMACON 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LTQ_SPI_IRNEN 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LTQ_SPI_ID_MOD_S 8 /* Module ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LTQ_SPI_CON_BM_S 16 /* Data width selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LTQ_SPI_CON_HB BIT(4) /* Heading control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LTQ_SPI_STAT_RXBV_S 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LTQ_SPI_WHBSTATE_CLRME | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LTQ_SPI_WHBSTATE_CLRTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LTQ_SPI_WHBSTATE_CLRRE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LTQ_SPI_WHBSTATE_CLRAE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LTQ_SPI_WHBSTATE_CLRTUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LTQ_SPI_FSTAT_RXFFL_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LTQ_SPI_FSTAT_TXFFL_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LTQ_SPI_GPOCON_ISCSBN_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LTQ_SPI_GPOCON_INVOUTN_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LTQ_SPI_FGPO_SETOUTN_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LTQ_SPI_FGPO_CLROUTN_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LTQ_SPI_IRNEN_ALL 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct lantiq_ssc_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct lantiq_ssc_hwcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int irnen_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int irnen_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int irncr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int irnicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 fifo_size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct lantiq_ssc_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk *spi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk *fpi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const struct lantiq_ssc_hwcfg *hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const u8 *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int tx_todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int rx_todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int base_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int fdx_tx_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return __raw_readl(spi->regbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __raw_writel(val, spi->regbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 set, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 val = __raw_readl(spi->regbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __raw_writel(val, spi->regbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return spi->tx_fifo_size - tx_fifo_level(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 spi_clk, brt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * SPI module clock is derived from FPI bus clock dependent on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * divider value in CLC.RMS which is always set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * f_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * baudrate = --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 2 * (BR + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spi_clk = clk_get_rate(spi->fpi_clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (max_speed_hz > spi_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) brt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) brt = spi_clk / max_speed_hz - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (brt > 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) brt = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spi_clk, max_speed_hz, brt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* CON.BM value = bits_per_word - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 con_set = 0, con_clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * SPI mode mapping in CON register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Mode CPOL CPHA CON.PO CON.PH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * 0 0 0 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * 1 0 1 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * 2 1 0 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * 3 1 1 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) con_clr |= LTQ_SPI_CON_PH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) con_set |= LTQ_SPI_CON_PH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Set heading control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) con_clr |= LTQ_SPI_CON_HB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) con_set |= LTQ_SPI_CON_HB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Set loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) con_set |= LTQ_SPI_CON_LB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) con_clr |= LTQ_SPI_CON_LB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Set clock divider for run mode to 1 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * run at same frequency as FPI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Put controller into config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) hw_enter_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Clear error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Enable error checking, disable TX/RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Setup default SPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hw_setup_bits_per_word(spi, spi->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hw_setup_clock_mode(spi, SPI_MODE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Enable master mode and clear error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) LTQ_SPI_WHBSTATE_CLR_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) LTQ_SPI_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Reset GPIO/CS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Enable and flush FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rx_fifo_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tx_fifo_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int lantiq_ssc_setup(struct spi_device *spidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct spi_master *master = spidev->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int cs = spidev->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 gpocon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* GPIOs are used for CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (spidev->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (cs < spi->base_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "chipselect %i too small (min %i)\n", cs, spi->base_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* set GPO pin to CS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* invert GPO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (spidev->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) gpocon |= 1 << (cs - spi->base_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int lantiq_ssc_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) hw_enter_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) hw_setup_clock_mode(spi, message->spi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hw_enter_active_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct spi_device *spidev, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (bits_per_word != spi->bits_per_word ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) speed_hz != spi->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hw_enter_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hw_setup_speed_hz(spi, speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) hw_setup_bits_per_word(spi, bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) hw_enter_active_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spi->speed_hz = speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spi->bits_per_word = bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Configure transmitter and receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (t->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) con &= ~LTQ_SPI_CON_TXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) con |= LTQ_SPI_CON_TXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) con &= ~LTQ_SPI_CON_RXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) con |= LTQ_SPI_CON_RXOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int lantiq_ssc_unprepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) flush_workqueue(spi->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Disable transmitter and receiver while idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) LTQ_SPI_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void tx_fifo_write(struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const u8 *tx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) const u16 *tx16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const u32 *tx32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int tx_free = tx_fifo_free(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spi->fdx_tx_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) while (spi->tx_todo && tx_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) switch (spi->bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case 2 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tx8 = spi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) data = *tx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) spi->tx_todo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spi->tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tx16 = (u16 *) spi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) data = *tx16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) spi->tx_todo -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spi->tx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tx32 = (u32 *) spi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) data = *tx32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spi->tx_todo -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) spi->tx += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tx_free--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spi->fdx_tx_level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 *rx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u16 *rx16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 *rx32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int rx_fill = rx_fifo_level(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Wait until all expected data to be shifted in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Otherwise, rx overrun may occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) while (rx_fill != spi->fdx_tx_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) rx_fill = rx_fifo_level(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) while (rx_fill) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) switch (spi->bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case 2 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rx8 = spi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *rx8 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spi->rx_todo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spi->rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rx16 = (u16 *) spi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *rx16 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) spi->rx_todo -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) spi->rx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rx32 = (u32 *) spi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *rx32 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spi->rx_todo -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spi->rx += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rx_fill--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 data, *rx32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 *rx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int rxbv, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int rx_fill = rx_fifo_level(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * In RX-only mode the bits per word value is ignored by HW. A value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * If remaining RX bytes are less than 4, the FIFO must be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * differently. The amount of received and valid bytes is indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * by STAT.RXBV register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) while (rx_fill) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (spi->rx_todo < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) shift = (rxbv - 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rx8 = spi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) while (rxbv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *rx8++ = (data >> shift) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rxbv--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) shift -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) spi->rx_todo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spi->rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rx32 = (u32 *) spi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *rx32++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spi->rx_todo -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) spi->rx += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rx_fill--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void rx_request(struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int rxreq, rxreq_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * To avoid receive overflows at high clocks it is better to request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * only the amount of bytes that fits into all FIFOs. This value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * depends on the FIFO size implemented in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rxreq = spi->rx_todo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rxreq_max = spi->rx_fifo_size * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (rxreq > rxreq_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rxreq = rxreq_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct lantiq_ssc_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) spin_lock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (hwcfg->irq_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) lantiq_ssc_writel(spi, val, hwcfg->irncr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (spi->tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (spi->rx && spi->rx_todo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) rx_fifo_read_full_duplex(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (spi->tx_todo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) tx_fifo_write(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else if (!tx_fifo_level(spi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else if (spi->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (spi->rx_todo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rx_fifo_read_half_duplex(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (spi->rx_todo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rx_request(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) goto completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) completed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) queue_work(spi->wq, &spi->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct lantiq_ssc_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!(stat & LTQ_SPI_STAT_ERRORS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) spin_lock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (hwcfg->irq_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) lantiq_ssc_writel(spi, val, hwcfg->irncr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (stat & LTQ_SPI_STAT_RUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(spi->dev, "receive underflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (stat & LTQ_SPI_STAT_TUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(spi->dev, "transmit underflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (stat & LTQ_SPI_STAT_AE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(spi->dev, "abort error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (stat & LTQ_SPI_STAT_RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(spi->dev, "receive overflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (stat & LTQ_SPI_STAT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(spi->dev, "transmit overflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (stat & LTQ_SPI_STAT_ME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_err(spi->dev, "mode error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Clear error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* set bad status so it can be retried */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (spi->master->cur_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spi->master->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) queue_work(spi->wq, &spi->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) spin_unlock(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static irqreturn_t intel_lgm_ssc_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct lantiq_ssc_spi *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!(val & LTQ_SPI_IRNEN_ALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (val & LTQ_SPI_IRNEN_E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return lantiq_ssc_err_interrupt(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if ((val & hwcfg->irnen_t) || (val & hwcfg->irnen_r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return lantiq_ssc_xmit_interrupt(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) spin_lock_irqsave(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spi->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) spi->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) spi->tx_todo = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* initially fill TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tx_fifo_write(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (spi->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) spi->rx_todo = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* start shift clock in RX-only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!spi->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rx_request(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) spin_unlock_irqrestore(&spi->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * The driver only gets an interrupt when the FIFO is empty, but there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * is an additional shift register from which the data is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * the wire. We get the last interrupt when the controller starts to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * write the last word to the wire, not when it is finished. Do busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * waiting till it finishes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void lantiq_ssc_bussy_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct lantiq_ssc_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned long long timeout = 8LL * 1000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) spi = container_of(work, typeof(*spi), work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) do_div(timeout, spi->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) timeout += timeout + 100; /* some tolerance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) end = jiffies + msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!(stat & LTQ_SPI_STAT_BSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) spi_finalize_current_transfer(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } while (!time_after_eq(jiffies, end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (spi->master->cur_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spi->master->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spi_finalize_current_transfer(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void lantiq_ssc_handle_err(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* flush FIFOs on timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) rx_fifo_flush(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) tx_fifo_flush(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned int cs = spidev->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 fgpo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!!(spidev->mode & SPI_CS_HIGH) == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fgpo = (1 << (cs - spi->base_cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int lantiq_ssc_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct spi_device *spidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hw_setup_transfer(spi, spidev, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return transfer_start(spi, spidev, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 0, LTQ_SPI_RX_IRQ_NAME, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 0, LTQ_SPI_TX_IRQ_NAME, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_err_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 0, LTQ_SPI_ERR_IRQ_NAME, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .cfg_irq = lantiq_cfg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .irnicr = 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .irncr = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .fifo_size_mask = GENMASK(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .irq_ack = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .cfg_irq = lantiq_cfg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .irnen_r = LTQ_SPI_IRNEN_R_XRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .irnen_t = LTQ_SPI_IRNEN_T_XRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .irnicr = 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .irncr = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .fifo_size_mask = GENMASK(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .irq_ack = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const struct lantiq_ssc_hwcfg intel_ssc_lgm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .cfg_irq = intel_lgm_cfg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .irnen_r = LTQ_SPI_IRNEN_R_XRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .irnen_t = LTQ_SPI_IRNEN_T_XRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .irnicr = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .irncr = 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .fifo_size_mask = GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .irq_ack = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct of_device_id lantiq_ssc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int lantiq_ssc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct lantiq_ssc_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) const struct lantiq_ssc_hwcfg *hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 id, supports_dma, revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned int num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) match = of_match_device(lantiq_ssc_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(dev, "no device match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hwcfg = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) spi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) spi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) spi->hwcfg = hwcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) platform_set_drvdata(pdev, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) spi->regbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (IS_ERR(spi->regbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) err = PTR_ERR(spi->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = hwcfg->cfg_irq(pdev, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spi->spi_clk = devm_clk_get(dev, "gate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (IS_ERR(spi->spi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) err = PTR_ERR(spi->spi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) err = clk_prepare_enable(spi->spi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) goto err_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Use the old clk_get_fpi() function on Lantiq platform, till it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * supports common clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) spi->fpi_clk = clk_get_fpi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) spi->fpi_clk = clk_get(dev, "freq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (IS_ERR(spi->fpi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) err = PTR_ERR(spi->fpi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) num_cs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) spi->base_cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) spin_lock_init(&spi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) spi->speed_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) master->setup = lantiq_ssc_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) master->set_cs = lantiq_ssc_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) master->handle_err = lantiq_ssc_handle_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) master->prepare_message = lantiq_ssc_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) master->unprepare_message = lantiq_ssc_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) master->transfer_one = lantiq_ssc_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) SPI_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (!spi->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) revision = id & LTQ_SPI_ID_REV_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) lantiq_ssc_hw_init(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) err = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(dev, "failed to register spi_master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto err_wq_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) err_wq_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) destroy_workqueue(spi->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) clk_put(spi->fpi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clk_disable_unprepare(spi->spi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) err_master_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int lantiq_ssc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) rx_fifo_flush(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) tx_fifo_flush(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) hw_enter_config_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) destroy_workqueue(spi->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) clk_disable_unprepare(spi->spi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clk_put(spi->fpi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static struct platform_driver lantiq_ssc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .probe = lantiq_ssc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .remove = lantiq_ssc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .name = "spi-lantiq-ssc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .of_match_table = lantiq_ssc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) module_platform_driver(lantiq_ssc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) MODULE_ALIAS("platform:spi-lantiq-ssc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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