^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2008 Juergen Beisert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_NAME "spi_imx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static bool use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(use_dma, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXC_CSPIRXDATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXC_CSPITXDATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXC_CSPICTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MXC_CSPIINT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXC_RESET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* generic defines to abstract from the different register layouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* The maximum bytes that a sdma BD can transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_SDMA_BD_BYTES (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MX51_ECSPI_CTRL_MAX_BURST 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MX53_MAX_TRANSFER_BYTES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum spi_imx_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IMX1_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IMX21_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IMX27_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IMX31_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IMX35_CSPI, /* CSPI on all i.mx except above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IMX51_ECSPI, /* ECSPI on i.mx51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IMX53_ECSPI, /* ECSPI on i.mx53 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct spi_imx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct spi_imx_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void (*intctrl)(struct spi_imx_data *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void (*trigger)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int (*rx_available)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void (*reset)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void (*setup_wml)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void (*disable)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void (*disable_dma)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool has_dmamode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool has_slavemode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool dynamic_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum spi_imx_devtype devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct spi_imx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long spi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int spi_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int spi_drctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int count, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void (*tx)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void (*rx)(struct spi_imx_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const void *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int txfifo; /* number of words pushed in tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int dynamic_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool slave_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int slave_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool usedma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 wml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct completion dma_rx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct completion dma_tx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct spi_imx_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline int is_imx27_cspi(struct spi_imx_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return d->devtype_data->devtype == IMX27_CSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline int is_imx35_cspi(struct spi_imx_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return d->devtype_data->devtype == IMX35_CSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline int is_imx51_ecspi(struct spi_imx_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return d->devtype_data->devtype == IMX51_ECSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline int is_imx53_ecspi(struct spi_imx_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return d->devtype_data->devtype == IMX53_ECSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MXC_SPI_BUF_RX(type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (spi_imx->rx_buf) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *(type *)spi_imx->rx_buf = val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spi_imx->rx_buf += sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) spi_imx->remainder -= sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MXC_SPI_BUF_TX(type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) type val = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (spi_imx->tx_buf) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = *(type *)spi_imx->tx_buf; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spi_imx->tx_buf += sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spi_imx->count -= sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(val, spi_imx->base + MXC_CSPITXDATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MXC_SPI_BUF_RX(u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MXC_SPI_BUF_TX(u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MXC_SPI_BUF_RX(u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MXC_SPI_BUF_TX(u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MXC_SPI_BUF_RX(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MXC_SPI_BUF_TX(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * (which is currently not the case in this driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 256, 384, 512, 768, 1024};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* MX21, MX27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int spi_imx_clkdiv_1(unsigned int fin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int fspi, unsigned int max, unsigned int *fres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 2; i < max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (fspi * mxc_clkdivs[i] >= fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *fres = fin / mxc_clkdivs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* MX1, MX31, MX35, MX51 CSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static unsigned int spi_imx_clkdiv_2(unsigned int fin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int fspi, unsigned int *fres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int i, div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (fspi * div >= fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) div <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *fres = fin / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int spi_imx_bytes_per_word(const int bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (bits_per_word <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else if (bits_per_word <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!use_dma || master->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!master->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (spi_imx->slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (transfer->len < spi_imx->devtype_data->fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spi_imx->dynamic_burst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MX51_ECSPI_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MX51_ECSPI_CTRL_XCH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MX51_ECSPI_CTRL_SMC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MX51_ECSPI_CTRL_BL_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MX51_ECSPI_CONFIG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MX51_ECSPI_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MX51_ECSPI_INT_TEEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MX51_ECSPI_INT_RREN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MX51_ECSPI_INT_RDREN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MX51_ECSPI_DMA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MX51_ECSPI_DMA_TEDEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MX51_ECSPI_DMA_RXDEN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MX51_ECSPI_STAT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MX51_ECSPI_STAT_RR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MX51_ECSPI_TESTREG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MX51_ECSPI_TESTREG_LBC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (spi_imx->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (bytes_per_word == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) val = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else if (bytes_per_word == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val = (val << 16) | (val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *(u32 *)spi_imx->rx_buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spi_imx->rx_buf += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) spi_imx->remainder -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int unaligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unaligned = spi_imx->remainder % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!unaligned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spi_imx_buf_rx_swap_u32(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spi_imx_buf_rx_u16(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val = readl(spi_imx->base + MXC_CSPIRXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (unaligned--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (spi_imx->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spi_imx->rx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spi_imx->remainder--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (spi_imx->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) val = *(u32 *)spi_imx->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spi_imx->tx_buf += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) spi_imx->count -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (bytes_per_word == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else if (bytes_per_word == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) val = (val << 16) | (val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(val, spi_imx->base + MXC_CSPITXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int unaligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unaligned = spi_imx->count % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!unaligned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spi_imx_buf_tx_swap_u32(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spi_imx_buf_tx_u16(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) while (unaligned--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (spi_imx->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spi_imx->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spi_imx->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(val, spi_imx->base + MXC_CSPITXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (spi_imx->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int n_bytes = spi_imx->slave_burst % sizeof(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!n_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) n_bytes = sizeof(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) memcpy(spi_imx->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spi_imx->rx_buf += n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spi_imx->slave_burst -= n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spi_imx->remainder -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int n_bytes = spi_imx->count % sizeof(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!n_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) n_bytes = sizeof(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (spi_imx->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spi_imx->tx_buf, n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spi_imx->tx_buf += n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spi_imx->count -= n_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(val, spi_imx->base + MXC_CSPITXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* MX51 eCSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int fspi, unsigned int *fres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * there are two 4-bit dividers, the pre-divider divides by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * $pre, the post-divider by 2^$post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int pre, post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int fin = spi_imx->spi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (unlikely(fspi > fin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) post = fls(fin) - fls(fspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (fin > fspi << post)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) post++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* now we have: (fin <= fspi << post) with post being minimal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) post = max(4U, post) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (unlikely(post > 0xf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) fspi, fin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pre = DIV_ROUND_UP(fin, fspi << post) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __func__, fin, fspi, post, pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Resulting frequency for the SCLK line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *fres = (fin / (pre + 1)) >> post;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (enable & MXC_INT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val |= MX51_ECSPI_INT_TEEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (enable & MXC_INT_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val |= MX51_ECSPI_INT_RREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (enable & MXC_INT_RDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val |= MX51_ECSPI_INT_RDREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writel(val, spi_imx->base + MX51_ECSPI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) reg |= MX51_ECSPI_CTRL_XCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void mx51_disable_dma(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writel(0, spi_imx->base + MX51_ECSPI_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct spi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 min_speed_hz = ~0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 testreg, delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* set Master or Slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (spi_imx->slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Enable SPI_RDY handling (falling edge/level triggered).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (spi->mode & SPI_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* set chip select to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * The ctrl register must be written first, with the EN bit set other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * registers must not be written to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) testreg |= MX51_ECSPI_TESTREG_LBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) testreg &= ~MX51_ECSPI_TESTREG_LBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * eCSPI burst completion by Chip Select signal in Slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * is not functional for imx53 Soc, config SPI burst completed when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * BURST_LENGTH + 1 bits are received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (spi->mode & SPI_CPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Wait until the changes in the configuration register CONFIGREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * propagate into the hardware. It takes exactly one tick of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * SCLK clock, but we will wait two SCLK clock just to be sure. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * effect of the delay it takes for the hardware to apply changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * is noticable if the SCLK clock run very slow. In such a case, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * the polarity of SCLK should be inverted, the GPIO ChipSelect might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * be asserted before the SCLK polarity changes, which would disrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * the SPI communication as the device on the other end would consider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * the change of SCLK polarity as a clock tick already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * callback, iterate over all the transfers in spi_message, find the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * one with lowest bus frequency, and use that bus frequency for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * delay calculation. In case all transfers have speed_hz == 0, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * min_speed_hz is ~0 and the resulting delay is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) list_for_each_entry(xfer, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!xfer->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) min_speed_hz = min(xfer->speed_hz, min_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) delay = (2 * 1000000) / min_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) udelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else /* SCLK is _very_ slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) usleep_range(delay, delay + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Clear BL field and set the right value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ctrl |= (spi_imx->slave_burst * 8 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) << MX51_ECSPI_CTRL_BL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ctrl |= (spi_imx->bits_per_word - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) << MX51_ECSPI_CTRL_BL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* set clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) spi_imx->spi_bus_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (spi_imx->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ctrl |= MX51_ECSPI_CTRL_SMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void mx51_setup_wml(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * Configure the DMA register: setup the watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * and enable DMA request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* drain receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) while (mx51_ecspi_rx_available(spi_imx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) readl(spi_imx->base + MXC_CSPIRXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define MX31_INTREG_TEEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MX31_INTREG_RREN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MX31_CSPICTRL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MX31_CSPICTRL_MASTER (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define MX31_CSPICTRL_XCH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MX31_CSPICTRL_SMC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MX31_CSPICTRL_POL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define MX31_CSPICTRL_PHA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define MX31_CSPICTRL_SSCTL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define MX31_CSPICTRL_SSPOL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define MX31_CSPICTRL_BC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define MX35_CSPICTRL_BL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define MX31_CSPICTRL_CS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define MX35_CSPICTRL_CS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define MX31_CSPICTRL_DR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define MX31_CSPI_DMAREG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define MX31_DMAREG_RH_DEN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MX31_DMAREG_TH_DEN (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define MX31_CSPISTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MX31_STATUS_RR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define MX31_CSPI_TESTREG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define MX31_TEST_LBC (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* These functions also work for the i.MX35, but be aware that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * the i.MX35 has a slightly different register layout for bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * we do not use here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (enable & MXC_INT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val |= MX31_INTREG_TEEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (enable & MXC_INT_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val |= MX31_INTREG_RREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel(val, spi_imx->base + MXC_CSPIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void mx31_trigger(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) reg = readl(spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) reg |= MX31_CSPICTRL_XCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int mx31_prepare_message(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned int clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MX31_CSPICTRL_DR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spi_imx->spi_bus_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (is_imx35_cspi(spi_imx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) reg |= MX31_CSPICTRL_SSCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) reg |= MX31_CSPICTRL_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) reg |= MX31_CSPICTRL_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) reg |= MX31_CSPICTRL_SSPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) reg |= (spi->chip_select) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MX31_CSPICTRL_CS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (spi_imx->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) reg |= MX31_CSPICTRL_SMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) reg |= MX31_TEST_LBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) reg &= ~MX31_TEST_LBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (spi_imx->usedma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * configure DMA requests when RXFIFO is half full and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * when TXFIFO is half empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) spi_imx->base + MX31_CSPI_DMAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int mx31_rx_available(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void mx31_reset(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* drain receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) readl(spi_imx->base + MXC_CSPIRXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MX21_INTREG_RR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MX21_INTREG_TEEN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MX21_INTREG_RREN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MX21_CSPICTRL_POL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MX21_CSPICTRL_PHA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MX21_CSPICTRL_SSPOL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MX21_CSPICTRL_XCH (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MX21_CSPICTRL_ENABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MX21_CSPICTRL_MASTER (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MX21_CSPICTRL_DR_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MX21_CSPICTRL_CS_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (enable & MXC_INT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) val |= MX21_INTREG_TEEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (enable & MXC_INT_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val |= MX21_INTREG_RREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) writel(val, spi_imx->base + MXC_CSPIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void mx21_trigger(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) reg = readl(spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) reg |= MX21_CSPICTRL_XCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int mx21_prepare_message(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) << MX21_CSPICTRL_DR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spi_imx->spi_bus_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) reg |= spi_imx->bits_per_word - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) reg |= MX21_CSPICTRL_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) reg |= MX21_CSPICTRL_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (spi->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) reg |= MX21_CSPICTRL_SSPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int mx21_rx_available(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static void mx21_reset(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) writel(1, spi_imx->base + MXC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define MX1_INTREG_RR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MX1_INTREG_TEEN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define MX1_INTREG_RREN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define MX1_CSPICTRL_POL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define MX1_CSPICTRL_PHA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define MX1_CSPICTRL_XCH (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define MX1_CSPICTRL_ENABLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define MX1_CSPICTRL_MASTER (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define MX1_CSPICTRL_DR_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (enable & MXC_INT_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val |= MX1_INTREG_TEEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (enable & MXC_INT_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) val |= MX1_INTREG_RREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writel(val, spi_imx->base + MXC_CSPIINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void mx1_trigger(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) reg = readl(spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) reg |= MX1_CSPICTRL_XCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int mx1_prepare_message(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned int clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MX1_CSPICTRL_DR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) spi_imx->spi_bus_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) reg |= spi_imx->bits_per_word - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) reg |= MX1_CSPICTRL_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) reg |= MX1_CSPICTRL_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) writel(reg, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int mx1_rx_available(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static void mx1_reset(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) writel(1, spi_imx->base + MXC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .intctrl = mx1_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .prepare_message = mx1_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .prepare_transfer = mx1_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .trigger = mx1_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .rx_available = mx1_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .reset = mx1_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .has_dmamode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .dynamic_burst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .has_slavemode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .devtype = IMX1_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .intctrl = mx21_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .prepare_message = mx21_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .prepare_transfer = mx21_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .trigger = mx21_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .rx_available = mx21_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .reset = mx21_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .has_dmamode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .dynamic_burst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .has_slavemode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .devtype = IMX21_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* i.mx27 cspi shares the functions with i.mx21 one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .intctrl = mx21_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .prepare_message = mx21_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .prepare_transfer = mx21_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .trigger = mx21_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .rx_available = mx21_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .reset = mx21_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .has_dmamode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .dynamic_burst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .has_slavemode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .devtype = IMX27_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .intctrl = mx31_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .prepare_message = mx31_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .prepare_transfer = mx31_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .trigger = mx31_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .rx_available = mx31_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .reset = mx31_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .has_dmamode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .dynamic_burst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .has_slavemode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .devtype = IMX31_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* i.mx35 and later cspi shares the functions with i.mx31 one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .intctrl = mx31_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .prepare_message = mx31_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .prepare_transfer = mx31_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .trigger = mx31_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .rx_available = mx31_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .reset = mx31_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .has_dmamode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .dynamic_burst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .has_slavemode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .devtype = IMX35_CSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .intctrl = mx51_ecspi_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .prepare_message = mx51_ecspi_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .prepare_transfer = mx51_ecspi_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .trigger = mx51_ecspi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .rx_available = mx51_ecspi_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .reset = mx51_ecspi_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .setup_wml = mx51_setup_wml,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .disable_dma = mx51_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .has_dmamode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .dynamic_burst = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .has_slavemode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .disable = mx51_ecspi_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .devtype = IMX51_ECSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .intctrl = mx51_ecspi_intctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .prepare_message = mx51_ecspi_prepare_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .prepare_transfer = mx51_ecspi_prepare_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .trigger = mx51_ecspi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .rx_available = mx51_ecspi_rx_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .disable_dma = mx51_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .reset = mx51_ecspi_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .fifo_size = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .has_dmamode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .has_slavemode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .disable = mx51_ecspi_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .devtype = IMX53_ECSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct platform_device_id spi_imx_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .name = "imx1-cspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .name = "imx21-cspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "imx27-cspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .name = "imx31-cspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .name = "imx35-cspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .name = "imx51-ecspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .name = "imx53-ecspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct of_device_id spi_imx_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static void spi_imx_push(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int burst_len, fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (spi_imx->dynamic_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) fifo_words = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Reload the FIFO when the remaining bytes to be transferred in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * current burst is 0. This only applies when bits_per_word is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * multiple of 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (!spi_imx->remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (spi_imx->dynamic_burst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* We need to deal unaligned data first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (!burst_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) burst_len = MX51_ECSPI_CTRL_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) spi_imx_set_burst_len(spi_imx, burst_len * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) spi_imx->remainder = burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) spi_imx->remainder = fifo_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (!spi_imx->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (spi_imx->dynamic_burst &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) fifo_words))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) spi_imx->tx(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) spi_imx->txfifo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (!spi_imx->slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) spi_imx->devtype_data->trigger(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static irqreturn_t spi_imx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct spi_imx_data *spi_imx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) while (spi_imx->txfifo &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) spi_imx->devtype_data->rx_available(spi_imx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) spi_imx->rx(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spi_imx->txfifo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (spi_imx->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) spi_imx_push(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (spi_imx->txfifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* No data left to push, but still waiting for rx data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * enable receive data available interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) spi_imx->devtype_data->intctrl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) spi_imx, MXC_INT_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) spi_imx->devtype_data->intctrl(spi_imx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) complete(&spi_imx->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static int spi_imx_dma_configure(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct dma_slave_config rx = {}, tx = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) tx.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) tx.dst_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) tx.dst_maxburst = spi_imx->wml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = dmaengine_slave_config(master->dma_tx, &tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) rx.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) rx.src_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) rx.src_maxburst = spi_imx->wml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = dmaengine_slave_config(master->dma_rx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int spi_imx_setupxfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!t->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!spi->max_speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_err(&spi->dev, "no speed_hz provided!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) spi_imx->spi_bus_clk = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) spi_imx->spi_bus_clk = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) spi_imx->bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * Initialize the functions for transfer. To transfer non byte-aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * words, we have to use multiple word-size bursts, we can't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * dynamic_burst in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) (spi_imx->bits_per_word == 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) spi_imx->bits_per_word == 16 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) spi_imx->bits_per_word == 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) spi_imx->rx = spi_imx_buf_rx_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) spi_imx->tx = spi_imx_buf_tx_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) spi_imx->dynamic_burst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (spi_imx->bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) spi_imx->rx = spi_imx_buf_rx_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) spi_imx->tx = spi_imx_buf_tx_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) } else if (spi_imx->bits_per_word <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spi_imx->rx = spi_imx_buf_rx_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) spi_imx->tx = spi_imx_buf_tx_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) spi_imx->rx = spi_imx_buf_rx_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) spi_imx->tx = spi_imx_buf_tx_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) spi_imx->dynamic_burst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) spi_imx->usedma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) spi_imx->usedma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) spi_imx->rx = mx53_ecspi_rx_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spi_imx->tx = mx53_ecspi_tx_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) spi_imx->slave_burst = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct spi_master *master = spi_imx->bitbang.master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (master->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dma_release_channel(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) master->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (master->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dma_release_channel(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) master->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* use pio mode for i.mx6dl chip TKT238285 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (of_machine_is_compatible("fsl,imx6dl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Prepare for TX DMA: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) master->dma_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (IS_ERR(master->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = PTR_ERR(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) master->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* Prepare for RX : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) master->dma_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (IS_ERR(master->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = PTR_ERR(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) master->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) init_completion(&spi_imx->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) init_completion(&spi_imx->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) master->can_dma = spi_imx_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) master->max_dma_len = MAX_SDMA_BD_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SPI_MASTER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) spi_imx_sdma_exit(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static void spi_imx_dma_rx_callback(void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) complete(&spi_imx->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void spi_imx_dma_tx_callback(void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) complete(&spi_imx->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) unsigned long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Time with actual data transfer and CS change delay related to HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Add extra second for scheduler related activities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) timeout += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* Double calculated timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct dma_async_tx_descriptor *desc_tx, *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) unsigned long transfer_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct spi_master *master = spi_imx->bitbang.master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) unsigned int bytes_per_word, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* Get the right burst length from the last sg to ensure no tail data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* Use 1 as wml in case no available burst length got */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) spi_imx->wml = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = spi_imx_dma_configure(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto dma_failure_no_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (!spi_imx->devtype_data->setup_wml) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(spi_imx->dev, "No setup_wml()?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto dma_failure_no_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) spi_imx->devtype_data->setup_wml(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * The TX DMA setup starts the transfer, so make sure RX is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * before TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) rx->sgl, rx->nents, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (!desc_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) goto dma_failure_no_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) desc_rx->callback = spi_imx_dma_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) desc_rx->callback_param = (void *)spi_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dmaengine_submit(desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) reinit_completion(&spi_imx->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dma_async_issue_pending(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) tx->sgl, tx->nents, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (!desc_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dmaengine_terminate_all(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dmaengine_terminate_all(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) desc_tx->callback = spi_imx_dma_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) desc_tx->callback_param = (void *)spi_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dmaengine_submit(desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) reinit_completion(&spi_imx->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dma_async_issue_pending(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Wait SDMA to finish the data transfer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) transfer_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dmaengine_terminate_all(master->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dmaengine_terminate_all(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) transfer_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_err(&master->dev, "I/O Error in DMA RX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) spi_imx->devtype_data->reset(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dmaengine_terminate_all(master->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* fallback to pio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dma_failure_no_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) transfer->error |= SPI_TRANS_FAIL_NO_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static int spi_imx_pio_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) unsigned long transfer_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) spi_imx->tx_buf = transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) spi_imx->rx_buf = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) spi_imx->count = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) spi_imx->txfifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) spi_imx->remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) reinit_completion(&spi_imx->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) spi_imx_push(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) transfer_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_err(&spi->dev, "I/O Error in PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) spi_imx->devtype_data->reset(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int spi_imx_pio_transfer_slave(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int ret = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (is_imx53_ecspi(spi_imx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) transfer->len > MX53_MAX_TRANSFER_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) MX53_MAX_TRANSFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) spi_imx->tx_buf = transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) spi_imx->rx_buf = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) spi_imx->count = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) spi_imx->txfifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) spi_imx->remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) reinit_completion(&spi_imx->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) spi_imx->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) spi_imx_push(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) spi_imx->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_dbg(&spi->dev, "interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* ecspi has a HW issue when works in Slave mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * ECSPI_TXDATA keeps shift out the last word data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * so we have to disable ECSPI when in slave mode after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * transfer completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (spi_imx->devtype_data->disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) spi_imx->devtype_data->disable(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int spi_imx_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) transfer->effective_speed_hz = spi_imx->spi_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* flush rxfifo before transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) while (spi_imx->devtype_data->rx_available(spi_imx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) readl(spi_imx->base + MXC_CSPIRXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (spi_imx->slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return spi_imx_pio_transfer_slave(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (spi_imx->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return spi_imx_dma_transfer(spi_imx, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return spi_imx_pio_transfer(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int spi_imx_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spi->mode, spi->bits_per_word, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static void spi_imx_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = pm_runtime_get_sync(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pm_runtime_put_noidle(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(spi_imx->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) pm_runtime_mark_last_busy(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pm_runtime_put_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) pm_runtime_mark_last_busy(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) pm_runtime_put_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static int spi_imx_slave_abort(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) spi_imx->slave_aborted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) complete(&spi_imx->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static int spi_imx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) of_match_device(spi_imx_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct spi_imx_data *spi_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int ret, irq, spi_drctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) bool slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) slave_mode = devtype_data->has_slavemode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) of_property_read_bool(np, "spi-slave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (slave_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) master = spi_alloc_slave(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) sizeof(struct spi_imx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) master = spi_alloc_master(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) sizeof(struct spi_imx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if ((ret < 0) || (spi_drctl >= 0x3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* '11' is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) spi_drctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) master->bus_num = np ? -1 : pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) spi_imx->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) spi_imx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) spi_imx->slave_mode = slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) spi_imx->devtype_data = devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * Get number of chip selects from device properties. This can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * coming from device tree or boardfiles, if it is not defined,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * a default value of 3 chip selects will be used, as all the legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * board files have <= 3 chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) master->num_chipselect = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) master->num_chipselect = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) spi_imx->bitbang.master->setup = spi_imx_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) | SPI_NO_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) is_imx53_ecspi(spi_imx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) spi_imx->spi_drctl = spi_drctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) init_completion(&spi_imx->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (IS_ERR(spi_imx->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ret = PTR_ERR(spi_imx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) spi_imx->base_phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) dev_name(&pdev->dev), spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (IS_ERR(spi_imx->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ret = PTR_ERR(spi_imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (IS_ERR(spi_imx->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ret = PTR_ERR(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ret = clk_prepare_enable(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) goto out_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ret = clk_prepare_enable(spi_imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) goto out_put_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) pm_runtime_use_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) pm_runtime_get_noresume(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) pm_runtime_set_active(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) pm_runtime_enable(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * Only validated on i.mx35 and i.mx6 now, can remove the constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * if validated on other chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (spi_imx->devtype_data->has_dmamode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) goto out_runtime_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) spi_imx->devtype_data->reset(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) spi_imx->devtype_data->intctrl(spi_imx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ret = spi_bitbang_start(&spi_imx->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto out_bitbang_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) pm_runtime_mark_last_busy(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) pm_runtime_put_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) out_bitbang_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (spi_imx->devtype_data->has_dmamode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) spi_imx_sdma_exit(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) out_runtime_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) pm_runtime_dont_use_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) pm_runtime_disable(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) clk_disable_unprepare(spi_imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) out_put_per:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) clk_disable_unprepare(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) out_master_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static int spi_imx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) spi_bitbang_stop(&spi_imx->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ret = pm_runtime_get_sync(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) pm_runtime_put_noidle(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dev_err(spi_imx->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) writel(0, spi_imx->base + MXC_CSPICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) pm_runtime_dont_use_autosuspend(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) pm_runtime_put_sync(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pm_runtime_disable(spi_imx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) spi_imx_sdma_exit(spi_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) struct spi_imx_data *spi_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ret = clk_prepare_enable(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ret = clk_prepare_enable(spi_imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) clk_disable_unprepare(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct spi_imx_data *spi_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) spi_imx = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) clk_disable_unprepare(spi_imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) clk_disable_unprepare(spi_imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static int __maybe_unused spi_imx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int __maybe_unused spi_imx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const struct dev_pm_ops imx_spi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) spi_imx_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static struct platform_driver spi_imx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .of_match_table = spi_imx_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .pm = &imx_spi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .id_table = spi_imx_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .probe = spi_imx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .remove = spi_imx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) module_platform_driver(spi_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) MODULE_DESCRIPTION("SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) MODULE_AUTHOR("Sascha Hauer, Pengutronix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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