^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: John Garry <john.garry@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HISI_SFC_V3XX_VERSION (0x1f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HISI_SFC_V3XX_INT_STAT (0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HISI_SFC_V3XX_INT_MASK (0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HISI_SFC_V3XX_INT_CLR (0x12c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HISI_SFC_V3XX_CMD_CFG (0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HISI_SFC_V3XX_CMD_INS (0x308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HISI_SFC_V3XX_CMD_ADDR (0x30c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Common definition of interrupt bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * protected address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HISI_SFC_V3XX_STD (0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HISI_SFC_V3XX_DIDO (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HISI_SFC_V3XX_DIO (2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HISI_SFC_V3XX_FULL_DIO (3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HISI_SFC_V3XX_QIQO (5 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HISI_SFC_V3XX_QIO (6 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HISI_SFC_V3XX_FULL_QIO (7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * an invalid mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { -EIO, -EIO, -EIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { -EIO, -EIO, -EIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct hisi_sfc_v3xx_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int max_cmd_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct completion *completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * The interrupt status register indicates whether an error occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * after per operation. Check it, and clear the interrupts for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * next time judgement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hisi_sfc_v3xx_clear_int(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(host->dev, "fail to access protected address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(host->dev, "page program operation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * The other bits of the interrupt registers is not currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * used and probably not be triggered in this driver. When it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * happens, we regard it as an unsupported error here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) HISI_SFC_V3XX_WAIT_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_device *spi = mem->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct hisi_sfc_v3xx_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) uintptr_t addr = (uintptr_t)op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int max_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) host = spi_controller_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) max_byte_count = host->max_cmd_dword * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) op->data.nbytes = 4 - (addr % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else if (op->data.nbytes > max_byte_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) op->data.nbytes = max_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The controller only supports Standard SPI mode, Duall mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Quad mode. Double sanitize the ops here to avoid OOB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) op->addr.buswidth > 4 || op->cmd.buswidth > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return spi_mem_default_supports_op(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * DATABUF registers -so use __io{read,write}32_copy when possible. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * trailing bytes, copy them byte-by-byte from the DATABUF register, as we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * can't clobber outside the source/dest buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * For efficient data read/write, we try to put any start 32b unaligned data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 *to, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void __iomem *from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (IS_ALIGNED((uintptr_t)to, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int words = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __ioread32_copy(to, from, words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) len -= words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) to += words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) from += words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = __raw_readl(from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (i = 0; i < len; i++, val >>= 8, to++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *to = (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 val = __raw_readl(from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (j = 0; j < 4 && (j + (i * 4) < len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) to++, val >>= 8, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *to = (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const u8 *from, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void __iomem *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (IS_ALIGNED((uintptr_t)from, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int words = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __iowrite32_copy(to, from, words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) len -= words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) to += words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) from += words * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < len; i++, from++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val |= *from << i * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __raw_writel(val, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) for (j = 0; j < 4 && (j + (i * 4) < len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) from++, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val |= *from << j * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __raw_writel(val, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const struct spi_mem_op *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int len = op->data.nbytes, buswidth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (op->data.buswidth == 0 || op->data.buswidth == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) buswidth_mode = HISI_SFC_V3XX_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int data_idx, addr_idx, cmd_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data_idx = (op->data.buswidth - 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) addr_idx = op->addr.buswidth / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) cmd_idx = op->cmd.buswidth / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (buswidth_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return buswidth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) config |= buswidth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (op->data.dir != SPI_MEM_NO_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) HISI_SFC_V3XX_CMD_CFG_START_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const struct spi_mem_op *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_COMPLETION_ONSTACK(done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (host->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) host->completion = &done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hisi_sfc_v3xx_enable_int(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (op->data.dir == SPI_MEM_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (host->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = wait_for_completion_timeout(host->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hisi_sfc_v3xx_disable_int(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) host->completion = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = hisi_sfc_v3xx_wait_cmd_idle(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (hisi_sfc_v3xx_handle_completion(host) || ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct hisi_sfc_v3xx_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct spi_device *spi = mem->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 chip_select = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) host = spi_controller_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .supports_op = hisi_sfc_v3xx_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .exec_op = hisi_sfc_v3xx_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct hisi_sfc_v3xx_host *host = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hisi_sfc_v3xx_disable_int(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) complete(host->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int hisi_sfc_v3xx_buswidth_override_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * ACPI FW does not allow us to currently set the device buswidth, so quirk it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * depending on the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .callback = hisi_sfc_v3xx_dmi_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .callback = hisi_sfc_v3xx_dmi_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .callback = hisi_sfc_v3xx_dmi_quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct hisi_sfc_v3xx_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) host = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) host->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) host->regbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (IS_ERR(host->regbase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = PTR_ERR(host->regbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) host->irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (host->irq == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hisi_sfc_v3xx_disable_int(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (host->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "hisi-sfc-v3xx", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) host->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) host->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ctlr->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ctlr->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case 0x351:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) host->max_cmd_dword = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) host->max_cmd_dword = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = devm_spi_register_controller(dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) version, host->irq ? "irq" : "polling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err_put_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spi_master_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #if IS_ENABLED(CONFIG_ACPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {"HISI0341", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct platform_driver hisi_sfc_v3xx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "hisi-sfc-v3xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .probe = hisi_sfc_v3xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int __init hisi_sfc_v3xx_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void __exit hisi_sfc_v3xx_spi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) module_init(hisi_sfc_v3xx_spi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) module_exit(hisi_sfc_v3xx_spi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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