^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/qcom-geni-se.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* SPI SE specific registers and respective register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SE_SPI_CPHA 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CPHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SE_SPI_LOOPBACK 0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LOOPBACK_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NORMAL_MODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LOOPBACK_MSK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SE_SPI_CPOL 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPOL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SE_SPI_DEMUX_SEL 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SE_SPI_TRANS_CFG 0x25c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CS_TOGGLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SE_SPI_WORD_LEN 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WORD_LEN_MSK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIN_WORD_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SE_SPI_TX_TRANS_LEN 0x26c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SE_SPI_RX_TRANS_LEN 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TRANS_LEN_MSK GENMASK(23, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SE_SPI_PRE_POST_CMD_DLY 0x274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SE_SPI_DELAY_COUNTERS 0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPI_CS_CLK_DELAY_SHFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* M_CMD OP codes for SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPI_TX_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_RX_ONLY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPI_TX_RX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPI_CS_ASSERT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_CS_DEASSERT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPI_SCK_ONLY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* M_CMD params for SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPI_PRE_CMD_DELAY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TIMESTAMP_BEFORE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FRAGMENTATION BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TIMESTAMP_AFTER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define POST_CMD_DELAY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct spi_geni_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct geni_se se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 tx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 fifo_width_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 tx_wm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 last_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long cur_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long cur_sclk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int cur_bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int tx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int rx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct spi_transfer *cur_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct completion cs_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct completion cancel_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct completion abort_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int oversampling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool cs_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool abort_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int get_spi_clk_cfg(unsigned int speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct spi_geni_master *mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int *clk_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int *clk_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long sclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int actual_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = geni_se_clk_freq_match(&mas->se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) speed_hz * mas->oversampling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_idx, &sclk_freq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret, speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) actual_hz = sclk_freq / (mas->oversampling * *clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) actual_hz, sclk_freq, *clk_idx, *clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mas->cur_sclk_hz = sclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void handle_fifo_timeout(struct spi_master *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reinit_completion(&mas->cancel_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mas->cur_xfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) geni_se_cancel_m_cmd(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reinit_completion(&mas->abort_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) geni_se_abort_m_cmd(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * No need for a lock since SPI core has a lock and we never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * access this from an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mas->abort_failed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 m_irq, m_irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!mas->abort_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The only known case where a transfer times out and then a cancel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * times out then an abort times out is if something is blocking our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * interrupt handler from running. Avoid starting any new transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * until that sorts itself out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (m_irq & m_irq_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) m_irq & m_irq_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * If we're here the problem resolved itself so no need to check more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * on future transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mas->abort_failed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct spi_master *spi = dev_get_drvdata(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!(slv->mode & SPI_CS_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) set_flag = !set_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (set_flag == mas->cs_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pm_runtime_get_sync(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (spi_geni_is_abort_still_pending(mas)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(mas->dev, "Can't set chip select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mas->cs_flag = set_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reinit_completion(&mas->cs_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (set_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) handle_fifo_timeout(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pm_runtime_put(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int pack_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 word_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * If bits_per_word isn't a byte aligned value, set the packing to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * 1 SPI word per FIFO word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!(mas->fifo_width_bits % bits_per_word))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pack_words = mas->fifo_width_bits / bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pack_words = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(word_len, se->base + SE_SPI_WORD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long clk_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 clk_sel, m_clk_cfg, idx, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (clk_hz == mas->cur_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * SPI core clock gets configured with the requested frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * or the frequency closer to the requested frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * For that reason requested frequency is stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * cur_speed_hz and referred in the consecutive transfer instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * of calling clk_get_rate() API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mas->cur_speed_hz = clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_sel = idx & CLK_SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(clk_sel, se->base + SE_GENI_CLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Set BW quota for CPU as driver supports FIFO mode only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = geni_icc_set_bw(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int setup_fifo_params(struct spi_device *spi_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct spi_master *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 demux_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (mas->last_mode != spi_slv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (spi_slv->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) loopback_cfg = LOOPBACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (spi_slv->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cpol = CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (spi_slv->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) cpha = CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (spi_slv->mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) demux_output_inv = BIT(spi_slv->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) demux_sel = spi_slv->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mas->cur_bits_per_word = spi_slv->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) writel(cpha, se->base + SE_SPI_CPHA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(cpol, se->base + SE_SPI_CPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mas->last_mode = spi_slv->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int spi_geni_prepare_message(struct spi_master *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct spi_message *spi_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (spi_geni_is_abort_still_pending(mas))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = setup_fifo_params(spi_msg->spi, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(mas->dev, "Couldn't select mode %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int spi_geni_init(struct spi_geni_master *mas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int proto, major, minor, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 spi_tx_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm_runtime_get_sync(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) proto = geni_se_read_proto(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (proto != GENI_SE_SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(mas->dev, "Invalid proto %d\n", proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pm_runtime_put(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Width of Tx and Rx FIFO is same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Hardware programming guide suggests to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * RX FIFO RFR level to fifo_depth-2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Transmit an entire FIFO worth of data per IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mas->tx_wm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ver = geni_se_get_qup_hw_version(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) major = GENI_SE_VERSION_MAJOR(ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) minor = GENI_SE_VERSION_MINOR(ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (major == 1 && minor == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mas->oversampling = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mas->oversampling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) geni_se_select_mode(se, GENI_SE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* We always control CS manually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spi_tx_cfg &= ~CS_TOGGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pm_runtime_put(mas->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Calculate how many bytes we'll put in each FIFO word. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * transfer words don't pack cleanly into a FIFO word we'll just put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * one transfer word in each FIFO word. If they do pack we'll pack 'em.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (mas->fifo_width_bits % mas->cur_bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BITS_PER_BYTE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return mas->fifo_width_bits / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static bool geni_spi_handle_tx(struct spi_geni_master *mas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int max_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Stop the watermark IRQ if nothing to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!mas->cur_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (mas->tx_rem_bytes < max_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) max_bytes = mas->tx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) while (i < max_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int bytes_to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 fifo_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 *fifo_byte = (u8 *)&fifo_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (j = 0; j < bytes_to_write; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fifo_byte[j] = tx_buf[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mas->tx_rem_bytes -= max_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!mas->tx_rem_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void geni_spi_handle_rx(struct spi_geni_master *mas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 rx_fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int rx_last_byte_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (rx_fifo_status & RX_LAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (rx_last_byte_valid && rx_last_byte_valid < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Clear out the FIFO and bail if nowhere to put it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!mas->cur_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) readl(se->base + SE_GENI_RX_FIFOn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (mas->rx_rem_bytes < rx_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rx_bytes = mas->rx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) while (i < rx_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 fifo_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 *fifo_byte = (u8 *)&fifo_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned int bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (j = 0; j < bytes_to_read; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rx_buf[i++] = fifo_byte[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mas->rx_rem_bytes -= rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void setup_fifo_xfer(struct spi_transfer *xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct spi_geni_master *mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 mode, struct spi_master *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 m_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Ensure that our interrupt handler isn't still running from some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * prior command before we start messing with the hardware behind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * its back. We don't need to _keep_ the lock here since we're only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * worried about racing with out interrupt handler. The SPI core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * already handles making sure that we're not trying to do two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * transfers at once or setting a chip select and doing a transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * concurrently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * NOTE: we actually _can't_ hold the lock here because possibly we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * might call clk_set_rate() which needs to be able to sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (xfer->bits_per_word != mas->cur_bits_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spi_setup_word_len(mas, mode, xfer->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mas->cur_bits_per_word = xfer->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Speed and bits per word can be overridden per transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mas->tx_rem_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mas->rx_rem_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) len &= TRANS_LEN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mas->cur_xfer = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (xfer->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) m_cmd |= SPI_TX_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mas->tx_rem_bytes = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(len, se->base + SE_SPI_TX_TRANS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (xfer->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) m_cmd |= SPI_RX_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writel(len, se->base + SE_SPI_RX_TRANS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mas->rx_rem_bytes = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Lock around right before we start the transfer since our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * interrupt could come in at any time now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_lock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * TX_WATERMARK_REG should be set after SPI configuration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * setting up GENI SE engine, as driver starts data transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * for the watermark interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (m_cmd & SPI_TX_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (geni_spi_handle_tx(mas))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) spin_unlock_irq(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int spi_geni_transfer_one(struct spi_master *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct spi_device *slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (spi_geni_is_abort_still_pending(mas))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Terminate and return success for 0 byte length transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!xfer->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) setup_fifo_xfer(xfer, mas, slv->mode, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static irqreturn_t geni_spi_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct spi_master *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct geni_se *se = &mas->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 m_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!m_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) spin_lock(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) geni_spi_handle_rx(mas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (m_irq & M_TX_FIFO_WATERMARK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) geni_spi_handle_tx(mas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (m_irq & M_CMD_DONE_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (mas->cur_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) spi_finalize_current_transfer(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mas->cur_xfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * If this happens, then a CMD_DONE came before all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Tx buffer bytes were sent out. This is unusual, log
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * this condition and disable the WM interrupt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * prevent the system from stalling due an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * storm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * If this happens when all Rx bytes haven't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * received, log the condition. The only known time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * this can happen is if bits_per_word != 8 and some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * registers that expect xfer lengths in num spi_words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * weren't written correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (mas->tx_rem_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mas->tx_rem_bytes, mas->cur_bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (mas->rx_rem_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mas->rx_rem_bytes, mas->cur_bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) complete(&mas->cs_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (m_irq & M_CMD_CANCEL_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) complete(&mas->cancel_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (m_irq & M_CMD_ABORT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) complete(&mas->abort_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * It's safe or a good idea to Ack all of our our interrupts at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * end of the function. Specifically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * clearing Acks. Clearing at the end relies on nobody else having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * started a new transfer yet or else we could be clearing _their_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * done bit, but everyone grabs the spinlock before starting a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * to be "latched level" interrupts so it's important to clear them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * _after_ you've handled the condition and always safe to do so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * since they'll re-assert if they're still happening.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spin_unlock(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int spi_geni_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct spi_master *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct spi_geni_master *mas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) clk = devm_clk_get(dev, "se");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) spi = devm_spi_alloc_master(dev, sizeof(*mas));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) platform_set_drvdata(pdev, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mas->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mas->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mas->se.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mas->se.wrapper = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mas->se.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mas->se.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (IS_ERR(mas->se.opp_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return PTR_ERR(mas->se.opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* OPP table is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = dev_pm_opp_of_add_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret && ret != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_err(&pdev->dev, "invalid OPP table in device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) goto put_clkname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) spi->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) spi->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spi->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) spi->max_speed_hz = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spi->prepare_message = spi_geni_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) spi->transfer_one = spi_geni_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) spi->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) spi->handle_err = handle_fifo_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) spi->set_cs = spi_geni_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) init_completion(&mas->cs_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) init_completion(&mas->cancel_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) init_completion(&mas->abort_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) spin_lock_init(&mas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = geni_icc_get(&mas->se, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto spi_geni_probe_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Set the bus quota to a reasonable value for register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = geni_icc_set_bw(&mas->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto spi_geni_probe_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = spi_geni_init(mas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto spi_geni_probe_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) goto spi_geni_probe_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = spi_register_master(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto spi_geni_probe_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) spi_geni_probe_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) free_irq(mas->irq, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) spi_geni_probe_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_pm_opp_of_remove_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) put_clkname:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_pm_opp_put_clkname(mas->se.opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int spi_geni_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct spi_master *spi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Unregister _before_ disabling pm_runtime() so we stop transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spi_unregister_master(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) free_irq(mas->irq, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_pm_opp_of_remove_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_pm_opp_put_clkname(mas->se.opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct spi_master *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Drop the performance state vote */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_pm_opp_set_rate(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = geni_se_resources_off(&mas->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return geni_icc_disable(&mas->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct spi_master *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct spi_geni_master *mas = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = geni_icc_enable(&mas->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = geni_se_resources_on(&mas->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int __maybe_unused spi_geni_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct spi_master *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = spi_master_suspend(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) spi_master_resume(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int __maybe_unused spi_geni_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct spi_master *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = spi_master_resume(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct dev_pm_ops spi_geni_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) spi_geni_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const struct of_device_id spi_geni_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { .compatible = "qcom,geni-spi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct platform_driver spi_geni_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .probe = spi_geni_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .remove = spi_geni_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = "geni_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .pm = &spi_geni_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .of_match_table = spi_geni_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) module_platform_driver(spi_geni_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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