Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Freescale SPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Maintainer: Kumar Gala
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2006 Polycom, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright 2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * CPM SPI and QE buffer descriptors mode support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Copyright (c) 2009  MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * GRLIB support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Copyright (c) 2012 Aeroflex Gaisler AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * Author: Andreas Larsson <andreas@gaisler.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __SPI_FSL_SPI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __SPI_FSL_SPI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* SPI Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct fsl_spi_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	__be32 cap; /* TYPE_GRLIB specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u8 res1[0x1C];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	__be32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	__be32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	__be32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	__be32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	__be32 transmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	__be32 receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	__be32 slvsel; /* TYPE_GRLIB specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* SPI Controller mode register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	SPMODE_LOOP		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	SPMODE_DIV16		(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	SPMODE_REV		(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define	SPMODE_MS		(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define	SPMODE_ENABLE		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	SPMODE_LEN(x)		((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define	SPMODE_PM(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define	SPMODE_OP		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	SPMODE_CG(x)		((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* TYPE_GRLIB SPI Controller capability register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPCAP_SSEN(x)		(((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPCAP_SSSZ(x)		(((x) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPCAP_MAXWLEN(x)	(((x) >> 20) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * Default for SPI Mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  *	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* SPIE register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define	SPIE_NE		0x00000200	/* Not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define	SPIE_NF		0x00000100	/* Not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SPIM register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define	SPIM_NE		0x00000200	/* Not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define	SPIM_NF		0x00000100	/* Not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* __SPI_FSL_SPI_H__ */