Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Freescale SPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Maintainer: Kumar Gala
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 Polycom, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * CPM SPI and QE buffer descriptors mode support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (c) 2009  MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GRLIB support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Copyright (c) 2012 Aeroflex Gaisler AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Author: Andreas Larsson <andreas@gaisler.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifdef CONFIG_FSL_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Specific to the MPC8306/MPC8309 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMMR_SPI_CS_OFFSET 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SPI_BOOT_SEL_BIT   0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include "spi-fsl-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include "spi-fsl-cpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include "spi-fsl-spi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TYPE_FSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TYPE_GRLIB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct fsl_spi_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.type = TYPE_FSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.type = TYPE_GRLIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static const struct of_device_id of_fsl_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.compatible = "fsl,spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.data = &of_fsl_spi_fsl_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.compatible = "aeroflexgaisler,spictrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.data = &of_fsl_spi_grlib_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int fsl_spi_get_type(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		match = of_match_node(of_fsl_spi_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (match && match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return ((struct fsl_spi_match_data *)match->data)->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return TYPE_FSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void fsl_spi_change_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct spi_mpc8xxx_cs *cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	__be32 __iomem *mode = &reg_base->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Turn off IRQs locally to minimize time that SPI is disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Turn off SPI unit prior changing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* When in CPM mode, we need to reinit tx and rx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (mspi->flags & SPI_CPM_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		fsl_spi_cpm_reinit_txrx(mspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mpc8xxx_spi_write_reg(mode, cs->hw_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void fsl_spi_chipselect(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct fsl_spi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	pdata = spi->dev.parent->parent->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (value == BITBANG_CS_INACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (pdata->cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			pdata->cs_control(spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (value == BITBANG_CS_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		mpc8xxx_spi->rx_shift = cs->rx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		mpc8xxx_spi->tx_shift = cs->tx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		mpc8xxx_spi->get_rx = cs->get_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		mpc8xxx_spi->get_tx = cs->get_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		fsl_spi_change_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (pdata->cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			pdata->cs_control(spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				      int bits_per_word, int msb_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	*rx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	*tx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (msb_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			*rx_shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			*tx_shift = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		} else if (bits_per_word <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			*rx_shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			*tx_shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		if (bits_per_word <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			*rx_shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				     int bits_per_word, int msb_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	*rx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	*tx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (bits_per_word <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (msb_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			*rx_shift = 16; /* LSB in bit 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			*tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			*rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				struct mpc8xxx_spi *mpc8xxx_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				int bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	cs->rx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	cs->tx_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		cs->get_rx = mpc8xxx_spi_rx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		cs->get_tx = mpc8xxx_spi_tx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	} else if (bits_per_word <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		cs->get_rx = mpc8xxx_spi_rx_buf_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		cs->get_tx = mpc8xxx_spi_tx_buf_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	} else if (bits_per_word <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		cs->get_rx = mpc8xxx_spi_rx_buf_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		cs->get_tx = mpc8xxx_spi_tx_buf_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (mpc8xxx_spi->set_shifts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 					bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 					!(spi->mode & SPI_LSB_FIRST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mpc8xxx_spi->rx_shift = cs->rx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	mpc8xxx_spi->tx_shift = cs->tx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mpc8xxx_spi->get_rx = cs->get_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mpc8xxx_spi->get_tx = cs->get_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				int bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* QE uses Little Endian for words > 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * so transform all words > 8 into 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * Unfortnatly that doesn't work for LSB so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * reject these for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Note: 32 bits word, LSB works iff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * tfcr/rfcr is set to CPMFCR_GBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (spi->mode & SPI_LSB_FIRST &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	    bits_per_word > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (bits_per_word > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return 8; /* pretend its 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int fsl_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct mpc8xxx_spi *mpc8xxx_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u8 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	mpc8xxx_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* spi_transfer level calls that work per-word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (!bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (!hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 							   mpc8xxx_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 							   bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	else if (mpc8xxx_spi->flags & SPI_QE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 							  bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (bits_per_word < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (bits_per_word == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		bits_per_word = bits_per_word - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* mask out bits we are going to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				  | SPMODE_PM(0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	cs->hw_mode |= SPMODE_LEN(bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if ((mpc8xxx_spi->spibrg / hz) > 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		cs->hw_mode |= SPMODE_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		WARN_ONCE(pm > 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			  "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			  dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		if (pm > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			pm = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		pm--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	cs->hw_mode |= SPMODE_PM(pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	fsl_spi_change_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				struct spi_transfer *t, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	mspi->count = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* enable rx ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* transmit word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	word = mspi->get_tx(mspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			    bool is_dma_mapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct fsl_spi_reg __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	unsigned int len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	reg_base = mpc8xxx_spi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (bits_per_word > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		/* invalid length? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (len & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		len /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (bits_per_word > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		/* invalid length? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (len & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		len /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	mpc8xxx_spi->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	mpc8xxx_spi->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	reinit_completion(&mpc8xxx_spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (mpc8xxx_spi->flags & SPI_CPM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	wait_for_completion(&mpc8xxx_spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* disable rx ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (mpc8xxx_spi->flags & SPI_CPM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return mpc8xxx_spi->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int fsl_spi_do_one_msg(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			      struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct spi_transfer *t, *first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	unsigned int cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	const int nsecs = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int status, last_bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * In CPU mode, optimize large byte transfers to use larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * bits_per_word values to reduce number of interrupts taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			if (t->len < 256 || t->bits_per_word != 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			if ((t->len & 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				t->bits_per_word = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			else if ((t->len & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				t->bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* Don't allow changes if CS is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			first = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		if (first->speed_hz != t->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 				"speed_hz cannot change while CS is active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	last_bpw = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		if (cs_change || last_bpw != t->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			status = fsl_spi_setup_transfer(spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		last_bpw = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		if (cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		cs_change = t->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		if (t->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			status = -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		spi_transfer_delay_exec(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		if (cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (status || !cs_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		ndelay(nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	fsl_spi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int fsl_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	struct mpc8xxx_spi *mpc8xxx_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	struct fsl_spi_reg __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	bool initial_setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	u32 hw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (!spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		spi_set_ctldata(spi, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		initial_setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	mpc8xxx_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	reg_base = mpc8xxx_spi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	hw_mode = cs->hw_mode; /* Save original settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	/* mask out bits we are going to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			 | SPMODE_REV | SPMODE_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (!(spi->mode & SPI_LSB_FIRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		cs->hw_mode |= SPMODE_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		cs->hw_mode |= SPMODE_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	retval = fsl_spi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		cs->hw_mode = hw_mode; /* Restore settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		if (initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void fsl_spi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	spi_set_ctldata(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	/* We need handle RX first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (events & SPIE_NE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		if (mspi->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 			mspi->get_rx(rx_data, mspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if ((events & SPIE_NF) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		/* spin until TX is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		while (((events =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 			mpc8xxx_spi_read_reg(&reg_base->event)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 						SPIE_NF) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	/* Clear the events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	mpc8xxx_spi_write_reg(&reg_base->event, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	mspi->count -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (mspi->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		u32 word = mspi->get_tx(mspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		mpc8xxx_spi_write_reg(&reg_base->transmit, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		complete(&mspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	struct mpc8xxx_spi *mspi = context_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	u32 events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	/* Get interrupt events(tx/rx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	events = mpc8xxx_spi_read_reg(&reg_base->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	if (events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	if (mspi->flags & SPI_CPM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		fsl_spi_cpm_irq(mspi, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		fsl_spi_cpu_irq(mspi, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	u32 slvsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	u16 cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	if (spi->cs_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		gpiod_set_value(spi->cs_gpiod, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	} else if (cs < mpc8xxx_spi->native_chipselects) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void fsl_spi_grlib_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	int mbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	u32 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	mbits = SPCAP_MAXWLEN(capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	if (mbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		mpc8xxx_spi->max_bits_per_word = mbits + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	mpc8xxx_spi->native_chipselects = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (SPCAP_SSEN(capabilities)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	master->num_chipselect = mpc8xxx_spi->native_chipselects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	pdata->cs_control = fsl_spi_grlib_cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct spi_master *fsl_spi_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		struct resource *mem, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	struct mpc8xxx_spi *mpc8xxx_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	struct fsl_spi_reg __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	dev_set_drvdata(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	mpc8xxx_spi_probe(dev, mem, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	master->setup = fsl_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	master->cleanup = fsl_spi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	master->transfer_one_message = fsl_spi_do_one_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	mpc8xxx_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	mpc8xxx_spi->max_bits_per_word = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	mpc8xxx_spi->type = fsl_spi_get_type(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	ret = fsl_spi_cpm_init(mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		goto err_cpm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	if (IS_ERR(mpc8xxx_spi->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 		ret = PTR_ERR(mpc8xxx_spi->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	if (mpc8xxx_spi->type == TYPE_GRLIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		fsl_spi_grlib_probe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	master->bits_per_word_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 		SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	if (mpc8xxx_spi->set_shifts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 		/* 8 bits per word and MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 		mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 					&mpc8xxx_spi->tx_shift, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	/* Register for SPI Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 			       0, "fsl_spi", mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 		goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	reg_base = mpc8xxx_spi->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	/* SPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	mpc8xxx_spi_write_reg(&reg_base->command, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	/* Enable SPI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	if (mpc8xxx_spi->max_bits_per_word < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 		regval &= ~SPMODE_LEN(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 		regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 		regval |= SPMODE_OP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 		goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 		 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	return master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) err_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	fsl_spi_cpm_free(mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err_cpm_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void fsl_spi_cs_control(struct spi_device *spi, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	if (spi->cs_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		gpiod_set_value(spi->cs_gpiod, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 		struct device *dev = spi->dev.parent->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 		struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 		struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 		if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int of_fsl_spi_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	struct resource mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	int irq, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	bool spisel_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #if IS_ENABLED(CONFIG_FSL_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	struct mpc8xxx_spi_probe_info *pinfo = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	ret = of_mpc8xxx_spi_probe(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 	type = fsl_spi_get_type(&ofdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 	if (type == TYPE_FSL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 		struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #if IS_ENABLED(CONFIG_FSL_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 		pinfo = to_of_pinfo(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 		spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 		if (spisel_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 			pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 			if (!pinfo->immr_spi_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 				return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 		 * Handle the case where we have one hardwired (always selected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 		 * device on the first "chipselect". Else we let the core code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 		 * handle any GPIOs or native chip selects and assign the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 		 * appropriate callback for dealing with the CS lines. This isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 		 * supported on the GRLIB variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 		ret = gpiod_count(dev, "cs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 			ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 		if (ret == 0 && !spisel_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 			pdata->max_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 			pdata->max_chipselect = ret + spisel_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 			pdata->cs_control = fsl_spi_cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	ret = of_address_to_resource(np, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 		goto unmap_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	irq = platform_get_irq(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 		ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 		goto unmap_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	master = fsl_spi_probe(dev, &mem, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	return PTR_ERR_OR_ZERO(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unmap_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #if IS_ENABLED(CONFIG_FSL_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 	if (spisel_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 		iounmap(pinfo->immr_spi_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int of_fsl_spi_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 	struct spi_master *master = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	fsl_spi_cpm_free(mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static struct platform_driver of_fsl_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 		.name = "fsl_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 		.of_match_table = of_fsl_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	.probe		= of_fsl_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	.remove		= of_fsl_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #ifdef CONFIG_MPC832x_RDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)  * XXX XXX XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)  * only. The driver should go away soon, since newer MPC8323E-RDB's device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)  * tree can work with OpenFirmware driver. But for now we support old trees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)  * as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 	struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	if (!dev_get_platdata(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 	if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 	if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 	master = fsl_spi_probe(&pdev->dev, mem, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 	return PTR_ERR_OR_ZERO(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 	fsl_spi_cpm_free(mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_ALIAS("platform:mpc8xxx_spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct platform_driver mpc8xxx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 	.probe = plat_mpc8xxx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	.remove = plat_mpc8xxx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 		.name = "mpc8xxx_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static bool legacy_driver_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static void __init legacy_driver_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 	legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void __exit legacy_driver_unregister(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 	if (legacy_driver_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 	platform_driver_unregister(&mpc8xxx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static void __init legacy_driver_register(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void __exit legacy_driver_unregister(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #endif /* CONFIG_MPC832x_RDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int __init fsl_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 	legacy_driver_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 	return platform_driver_register(&of_fsl_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) module_init(fsl_spi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static void __exit fsl_spi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 	platform_driver_unregister(&of_fsl_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 	legacy_driver_unregister();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) module_exit(fsl_spi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MODULE_AUTHOR("Kumar Gala");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) MODULE_DESCRIPTION("Simple Freescale SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_LICENSE("GPL");