^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Freescale QuadSPI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2018 Bootlin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2018 exceet electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2018 Kontron Electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Transition to SPI MEM interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Boris Brezillon <bbrezillon@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Frieder Schrempf <frieder.schrempf@kontron.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Suresh Gupta <suresh.gupta@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Based on the original fsl-quadspi.c SPI NOR driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Author: Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * The driver only uses one single LUT entry, that is updated on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * each call of exec_op(). Index 0 is preset at boot with a basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * read operation, so let's use the last entry (15).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SEQID_LUT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Registers used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QUADSPI_MCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QUADSPI_MCR_MDIS_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QUADSPI_MCR_DDR_EN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QUADSPI_IPCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QUADSPI_IPCR_SEQID(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QUADSPI_FLSHCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QUADSPI_BUF0CR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QUADSPI_BUF1CR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QUADSPI_BUF2CR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QUADSPI_BUF3CR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QUADSPI_BFGENCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QUADSPI_BUF0IND 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QUADSPI_BUF1IND 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QUADSPI_BUF2IND 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QUADSPI_SFAR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QUADSPI_SMPR 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QUADSPI_SMPR_FSDLY_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QUADSPI_SMPR_FSPHS_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QUADSPI_SMPR_HSENA_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QUADSPI_RBCT 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QUADSPI_TBDR 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QUADSPI_SR 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QUADSPI_SR_IP_ACC_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QUADSPI_SR_AHB_ACC_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QUADSPI_FR 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QUADSPI_FR_TFF_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QUADSPI_RSER 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QUADSPI_RSER_TFIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QUADSPI_SPTRCLR 0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QUADSPI_SPTRCLR_IPPTRC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QUADSPI_SPTRCLR_BFPTRC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QUADSPI_SFA1AD 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QUADSPI_SFA2AD 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QUADSPI_SFB1AD 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QUADSPI_SFB2AD 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QUADSPI_RBDR(x) (0x200 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QUADSPI_LUTKEY 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QUADSPI_LCKCR 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QUADSPI_LCKER_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QUADSPI_LCKER_UNLOCK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QUADSPI_LUT_BASE 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QUADSPI_LUT_REG(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Instruction set for the LUT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LUT_STOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LUT_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LUT_ADDR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LUT_DUMMY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LUT_MODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LUT_MODE2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LUT_MODE4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LUT_FSL_READ 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LUT_FSL_WRITE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LUT_JMP_ON_CS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LUT_ADDR_DDR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LUT_MODE_DDR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LUT_MODE2_DDR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LUT_MODE4_DDR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LUT_FSL_READ_DDR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LUT_FSL_WRITE_DDR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LUT_DATA_LEARN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * The PAD definitions for LUT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * The pad stands for the number of IO lines [0:3].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * For example, the quad read needs four IO lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * so you should use LUT_PAD(4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LUT_PAD(x) (fls(x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Macro for constructing the LUT entries with the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * ---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * ---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LUT_DEF(idx, ins, pad, opr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Controller needs driver to swap endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Controller needs 4x internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QUADSPI_QUIRK_4X_INT_CLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * TKT253890, the controller needs the driver to fill the txfifo with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * 16 bytes at least to trigger a data transfer, even though the extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * data won't be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QUADSPI_QUIRK_TKT253890 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* TKT245618, the controller cannot wake up from wait mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QUADSPI_QUIRK_TKT245618 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * internally. No need to add it when setting SFXXAD and SFAR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Controller uses TDH bits in register QUADSPI_FLSHCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * They need to be set in accordance with the DDR/SDR mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct fsl_qspi_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int rxfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int txfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int invalid_mstrid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int ahb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) bool little_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct fsl_qspi_devtype_data vybrid_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .txfifo = SZ_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .little_endian = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct fsl_qspi_devtype_data imx6sx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .txfifo = SZ_512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .little_endian = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct fsl_qspi_devtype_data imx7d_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .txfifo = SZ_512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) QUADSPI_QUIRK_USE_TDH_SETTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .little_endian = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct fsl_qspi_devtype_data imx6ul_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .txfifo = SZ_512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) QUADSPI_QUIRK_USE_TDH_SETTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .little_endian = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct fsl_qspi_devtype_data ls1021a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .txfifo = SZ_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .quirks = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .little_endian = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct fsl_qspi_devtype_data ls2080a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .rxfifo = SZ_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .txfifo = SZ_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ahb_buf_size = SZ_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .invalid_mstrid = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .little_endian = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct fsl_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *ahb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 memmap_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct clk *clk, *clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct completion c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const struct fsl_qspi_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int selected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline int needs_swap_endian(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline int needs_4x_clock(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline int needs_fill_txfifo(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline int needs_amba_base_offset(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline int needs_tdh_setting(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * An IC bug makes it necessary to rearrange the 32-bit data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Later chips, such as IMX6SLX, have fixed this bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return needs_swap_endian(q) ? __swab32(a) : a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * R/W functions for big- or little-endian registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * The QSPI controller's endianness is independent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * the CPU core's endianness. So far, although the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * core is little-endian the QSPI controller can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * big-endian or little-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (q->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (q->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct fsl_qspi *q = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg = qspi_readl(q, q->iobase + QUADSPI_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) qspi_writel(q, reg, q->iobase + QUADSPI_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (reg & QUADSPI_FR_TFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) complete(&q->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static bool fsl_qspi_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (op->dummy.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (op->data.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * The number of instructions needed for the op, needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * to fit into a single LUT entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (op->addr.nbytes +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (op->dummy.nbytes ? 1:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (op->data.nbytes ? 1:0) > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Max 64 dummy clock cycles supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (op->dummy.nbytes &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Max data length, check controller limits and alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (op->data.dir == SPI_MEM_DATA_IN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (op->data.nbytes > q->devtype_data->ahb_buf_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) !IS_ALIGNED(op->data.nbytes, 8))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (op->data.dir == SPI_MEM_DATA_OUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) op->data.nbytes > q->devtype_data->txfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return spi_mem_default_supports_op(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 lutval[4] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int lutidx = 1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) op->cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * For some unknown reason, using LUT_ADDR doesn't work in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * cases (at least with only one byte long addresses), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * let's use LUT_MODE to write the address bytes one by one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < op->addr.nbytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) LUT_PAD(op->addr.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) addrbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (op->dummy.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) LUT_PAD(op->dummy.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) op->dummy.nbytes * 8 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) lutval[lutidx / 2] |= LUT_DEF(lutidx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) op->data.dir == SPI_MEM_DATA_IN ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) LUT_FSL_READ : LUT_FSL_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) LUT_PAD(op->data.buswidth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) lutidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* unlock LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* fill LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < ARRAY_SIZE(lutval); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* lock LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = clk_prepare_enable(q->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = clk_prepare_enable(q->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) clk_disable_unprepare(q->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (needs_wakeup_wait_mode(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cpu_latency_qos_add_request(&q->pm_qos_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (needs_wakeup_wait_mode(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cpu_latency_qos_remove_request(&q->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_disable_unprepare(q->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_disable_unprepare(q->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * If we have changed the content of the flash by writing or erasing, or if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * read from flash with a different offset into the page buffer, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * invalidate the AHB buffer. If we do not do so, we may read out the wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * data. The spec tells us reset the AHB domain and Serial Flash domain at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void fsl_qspi_invalidate(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * The minimum delay : 1 AHB + 2 SFCK clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Delay 1 us is enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long rate = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (q->selected == spi->chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (needs_4x_clock(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rate *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fsl_qspi_clk_disable_unprep(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = clk_set_rate(q->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = fsl_qspi_clk_prep_enable(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) q->selected = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) fsl_qspi_invalidate(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) memcpy_fromio(op->data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) memcpy(&val, op->data.buf.out + i, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) val = fsl_qspi_endian_xchg(q, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) qspi_writel(q, val, base + QUADSPI_TBDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (i < op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) memcpy(&val, op->data.buf.out + i, op->data.nbytes - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val = fsl_qspi_endian_xchg(q, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) qspi_writel(q, val, base + QUADSPI_TBDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (needs_fill_txfifo(q)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) for (i = op->data.nbytes; i < 16; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) qspi_writel(q, 0, base + QUADSPI_TBDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 *buf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val = fsl_qspi_endian_xchg(q, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) memcpy(buf + i, &val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (i < op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val = fsl_qspi_endian_xchg(q, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) memcpy(buf + i, &val, op->data.nbytes - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) init_completion(&q->c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Always start the sequence at the same index since we update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * the LUT at each exec_op() call. And also specify the DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * length, since it's has not been specified in the LUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) base + QUADSPI_IPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Wait for the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fsl_qspi_read_rxfifo(q, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 mask, u32 delay_us, u32 timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!q->devtype_data->little_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mask = (u32)cpu_to_be32(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int invalid_mstrid = q->devtype_data->invalid_mstrid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mutex_lock(&q->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* wait for the controller being ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) QUADSPI_SR_AHB_ACC_MASK), 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fsl_qspi_select_mem(q, mem->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (needs_amba_base_offset(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) addr_offset = q->memmap_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) qspi_writel(q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) q->selected * q->devtype_data->ahb_buf_size + addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) base + QUADSPI_SFAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) base + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) base + QUADSPI_SPTRCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) fsl_qspi_prepare_lut(q, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * If we have large chunks of data, we read them through the AHB bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * by accessing the mapped memory. In all other cases we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * IP commands to access the flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fsl_qspi_read_ahb(q, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) fsl_qspi_fill_txfifo(q, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) err = fsl_qspi_do_op(q, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Invalidate the data in the AHB buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fsl_qspi_invalidate(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mutex_unlock(&q->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (op->data.dir == SPI_MEM_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (op->data.nbytes > q->devtype_data->txfifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) op->data.nbytes = q->devtype_data->txfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (op->data.nbytes > q->devtype_data->ahb_buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) op->data.nbytes = q->devtype_data->ahb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int fsl_qspi_default_setup(struct fsl_qspi *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) void __iomem *base = q->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 reg, addr_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* disable and unprepare clock to avoid glitch pass to controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) fsl_qspi_clk_disable_unprep(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* the default frequency, we will change it later if necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = clk_set_rate(q->clk, 66000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = fsl_qspi_clk_prep_enable(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Reset the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) base + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Disable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) base + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * Previous boot stages (BootROM, bootloader) might have used DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * mode and did not clear the TDH bits. As we currently use SDR mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * only, clear the TDH bits if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (needs_tdh_setting(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ~QUADSPI_FLSHCR_TDH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) base + QUADSPI_FLSHCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg = qspi_readl(q, base + QUADSPI_SMPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) | QUADSPI_SMPR_FSPHS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) | QUADSPI_SMPR_HSENA_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* We only use the buffer3 for AHB read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) qspi_writel(q, 0, base + QUADSPI_BUF0IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) qspi_writel(q, 0, base + QUADSPI_BUF1IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) qspi_writel(q, 0, base + QUADSPI_BUF2IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) q->iobase + QUADSPI_BFGENCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) base + QUADSPI_BUF3CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (needs_amba_base_offset(q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) addr_offset = q->memmap_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * In HW there can be a maximum of four chips on two buses with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * two chip selects on each bus. We use four chip selects in SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * to differentiate between the four chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * SFB2AD accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) base + QUADSPI_SFA1AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) base + QUADSPI_SFA2AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) base + QUADSPI_SFB1AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) base + QUADSPI_SFB2AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) q->selected = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Enable the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) base + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* clear all interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* enable the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const char *fsl_qspi_get_name(struct spi_mem *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct device *dev = &mem->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * In order to keep mtdparts compatible with the old MTD driver at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * platform_device of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (of_get_available_child_count(q->dev->of_node) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return dev_name(q->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) name = devm_kasprintf(dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "%s-%d", dev_name(q->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mem->spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(dev, "failed to get memory for custom flash name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct spi_controller_mem_ops fsl_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .adjust_op_size = fsl_qspi_adjust_op_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .supports_op = fsl_qspi_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .exec_op = fsl_qspi_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .get_name = fsl_qspi_get_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int fsl_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct fsl_qspi *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) q = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) q->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) q->devtype_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!q->devtype_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) platform_set_drvdata(pdev, q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* find the resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) q->iobase = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (IS_ERR(q->iobase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = PTR_ERR(q->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "QuadSPI-memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) q->memmap_phy = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Since there are 4 cs, map size required is 4 times ahb_buf_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) q->ahb_addr = devm_ioremap(dev, q->memmap_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) (q->devtype_data->ahb_buf_size * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!q->ahb_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* find the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) q->clk_en = devm_clk_get(dev, "qspi_en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (IS_ERR(q->clk_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = PTR_ERR(q->clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) q->clk = devm_clk_get(dev, "qspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (IS_ERR(q->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = PTR_ERR(q->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = fsl_qspi_clk_prep_enable(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_err(dev, "can not enable the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto err_put_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* find the irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = devm_request_irq(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) fsl_qspi_irq_handler, 0, pdev->name, q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(dev, "failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mutex_init(&q->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ctlr->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ctlr->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ctlr->mem_ops = &fsl_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) fsl_qspi_default_setup(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ctlr->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = devm_spi_register_controller(dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mutex_destroy(&q->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) fsl_qspi_clk_disable_unprep(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) err_put_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(dev, "Freescale QuadSPI probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int fsl_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct fsl_qspi *q = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* disable the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) fsl_qspi_clk_disable_unprep(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mutex_destroy(&q->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int fsl_qspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int fsl_qspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct fsl_qspi *q = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) fsl_qspi_default_setup(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct of_device_id fsl_qspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const struct dev_pm_ops fsl_qspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .suspend = fsl_qspi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .resume = fsl_qspi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct platform_driver fsl_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .name = "fsl-quadspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .of_match_table = fsl_qspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .pm = &fsl_qspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .probe = fsl_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .remove = fsl_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) module_platform_driver(fsl_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MODULE_AUTHOR("Freescale Semiconductor Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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