^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale i.MX7ULP LPSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright 2018 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_NAME "fsl_lpspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* The maximum bytes that edma can transfer once.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* i.MX7ULP LPSPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX7ULP_VERID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX7ULP_PARAM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX7ULP_CR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX7ULP_SR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX7ULP_IER 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX7ULP_DER 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX7ULP_CFGR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX7ULP_CFGR1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX7ULP_DMR0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX7ULP_DMR1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX7ULP_CCR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX7ULP_FCR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX7ULP_FSR 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX7ULP_TCR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX7ULP_TDR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX7ULP_RSR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX7ULP_RDR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* General control register field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CR_RRF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CR_RTF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CR_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CR_MEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SR_MBF BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SR_TCF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SR_FCF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SR_RDF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SR_TDF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IER_TCIE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IER_FCIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IER_RDIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IER_TDIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DER_RDDE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DER_TDDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CFGR1_PCSCFG BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CFGR1_PINCFG (BIT(24)|BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CFGR1_PCSPOL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CFGR1_NOSTALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CFGR1_MASTER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FSR_TXCOUNT (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RSR_RXEMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TCR_CPOL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TCR_CPHA BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TCR_CONT BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TCR_CONTC BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TCR_RXMSK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TCR_TXMSK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct lpspi_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct fsl_lpspi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool is_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool is_only_cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool is_first_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const void *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void (*tx)(struct fsl_lpspi_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void (*rx)(struct fsl_lpspi_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 txfifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 rxfifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct lpspi_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool slave_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool usedma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct completion dma_rx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct completion dma_tx_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct of_device_id fsl_lpspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .compatible = "fsl,imx7ulp-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LPSPI_BUF_RX(type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (fsl_lpspi->rx_buf) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *(type *)fsl_lpspi->rx_buf = val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) fsl_lpspi->rx_buf += sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LPSPI_BUF_TX(type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) type val = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (fsl_lpspi->tx_buf) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = *(type *)fsl_lpspi->tx_buf; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) fsl_lpspi->tx_buf += sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fsl_lpspi->remain -= sizeof(type); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LPSPI_BUF_RX(u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) LPSPI_BUF_TX(u8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LPSPI_BUF_RX(u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) LPSPI_BUF_TX(u16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) LPSPI_BUF_RX(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) LPSPI_BUF_TX(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(enable, fsl_lpspi->base + IMX7ULP_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int fsl_lpspi_bytes_per_word(const int bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static bool fsl_lpspi_can_dma(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!controller->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) switch (bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(fsl_lpspi->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pm_runtime_mark_last_busy(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pm_runtime_put_autosuspend(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 txfifo_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) while (txfifo_cnt < fsl_lpspi->txfifosize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!fsl_lpspi->remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fsl_lpspi->tx(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) txfifo_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (txfifo_cnt < fsl_lpspi->txfifosize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!fsl_lpspi->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) temp &= ~TCR_CONTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) fsl_lpspi->rx(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) temp |= fsl_lpspi->config.bpw - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) temp |= (fsl_lpspi->config.mode & 0x3) << 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!fsl_lpspi->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) temp |= fsl_lpspi->config.prescale << 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Set TCR_CONT will keep SS asserted after current transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * For the first transfer, clear TCR_CONTC to assert SS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * For subsequent transfer, set TCR_CONTC to keep SS asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!fsl_lpspi->usedma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) temp |= TCR_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (fsl_lpspi->is_first_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) temp &= ~TCR_CONTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) temp |= TCR_CONTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!fsl_lpspi->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) temp = fsl_lpspi->watermark >> 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (fsl_lpspi->watermark >> 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) temp = fsl_lpspi->watermark >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct lpspi_config config = fsl_lpspi->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int perclk_rate, scldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (config.speed_hz > perclk_rate / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(fsl_lpspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "per-clk should be at least two times of transfer speed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (prescale = 0; prescale < 8; prescale++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (scldiv < 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) fsl_lpspi->config.prescale = prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (scldiv >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fsl_lpspi->base + IMX7ULP_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) perclk_rate, config.speed_hz, prescale, scldiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int fsl_lpspi_dma_configure(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct dma_slave_config rx = {}, tx = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tx.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) tx.dst_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tx.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = dmaengine_slave_config(controller->dma_tx, &tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rx.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rx.src_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rx.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = dmaengine_slave_config(controller->dma_rx, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!fsl_lpspi->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = fsl_lpspi_set_bitrate(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fsl_lpspi_set_watermark(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!fsl_lpspi->is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) temp = CFGR1_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) temp = CFGR1_PINCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (fsl_lpspi->config.mode & SPI_CS_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) temp |= CFGR1_PCSPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) temp = readl(fsl_lpspi->base + IMX7ULP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) temp |= CR_RRF | CR_RTF | CR_MEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel(temp, fsl_lpspi->base + IMX7ULP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (fsl_lpspi->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) temp = DER_TDDE | DER_RDDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) writel(temp, fsl_lpspi->base + IMX7ULP_DER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (t == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fsl_lpspi->config.mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fsl_lpspi->config.bpw = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) fsl_lpspi->config.speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (fsl_lpspi->is_only_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) fsl_lpspi->config.chip_select = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fsl_lpspi->config.chip_select = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!fsl_lpspi->config.speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) fsl_lpspi->config.speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!fsl_lpspi->config.bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) fsl_lpspi->config.bpw = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Initialize the functions for transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (fsl_lpspi->config.bpw <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else if (fsl_lpspi->config.bpw <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (t->len <= fsl_lpspi->txfifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fsl_lpspi->watermark = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) fsl_lpspi->watermark = fsl_lpspi->txfifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (fsl_lpspi_can_dma(controller, spi, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) fsl_lpspi->usedma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) fsl_lpspi->usedma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return fsl_lpspi_config(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int fsl_lpspi_slave_abort(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fsl_lpspi->slave_aborted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!fsl_lpspi->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) complete(&fsl_lpspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) complete(&fsl_lpspi->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) complete(&fsl_lpspi->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (fsl_lpspi->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) fsl_lpspi->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_dbg(fsl_lpspi->dev, "interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!fsl_lpspi->usedma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Disable all interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) fsl_lpspi_intctrl(fsl_lpspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* W1C for all flags in SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) temp = 0x3F << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel(temp, fsl_lpspi->base + IMX7ULP_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Clear FIFO and disable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) temp = CR_RRF | CR_RTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) writel(temp, fsl_lpspi->base + IMX7ULP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void fsl_lpspi_dma_rx_callback(void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) complete(&fsl_lpspi->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void fsl_lpspi_dma_tx_callback(void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) complete(&fsl_lpspi->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Time with actual data transfer and CS change delay related to HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Add extra second for scheduler related activities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) timeout += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Double calculated timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct fsl_lpspi_data *fsl_lpspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct dma_async_tx_descriptor *desc_tx, *desc_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned long transfer_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = fsl_lpspi_dma_configure(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rx->sgl, rx->nents, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!desc_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) desc_rx->callback = fsl_lpspi_dma_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) desc_rx->callback_param = (void *)fsl_lpspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dmaengine_submit(desc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reinit_completion(&fsl_lpspi->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dma_async_issue_pending(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tx->sgl, tx->nents, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!desc_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dmaengine_terminate_all(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) desc_tx->callback = fsl_lpspi_dma_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) desc_tx->callback_param = (void *)fsl_lpspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dmaengine_submit(desc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) reinit_completion(&fsl_lpspi->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dma_async_issue_pending(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) fsl_lpspi->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!fsl_lpspi->is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) transfer->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Wait eDMA to finish the data transfer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) transfer_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dmaengine_terminate_all(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dmaengine_terminate_all(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) transfer_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dmaengine_terminate_all(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dmaengine_terminate_all(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fsl_lpspi->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(fsl_lpspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "I/O Error in DMA TX interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dmaengine_terminate_all(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dmaengine_terminate_all(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fsl_lpspi->slave_aborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_dbg(fsl_lpspi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "I/O Error in DMA RX interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dmaengine_terminate_all(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dmaengine_terminate_all(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void fsl_lpspi_dma_exit(struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (controller->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_release_channel(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) controller->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (controller->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dma_release_channel(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) controller->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int fsl_lpspi_dma_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct fsl_lpspi_data *fsl_lpspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct spi_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Prepare for TX DMA: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) controller->dma_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (IS_ERR(controller->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = PTR_ERR(controller->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) controller->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Prepare for RX DMA: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) controller->dma_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (IS_ERR(controller->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = PTR_ERR(controller->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) controller->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) init_completion(&fsl_lpspi->dma_rx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) init_completion(&fsl_lpspi->dma_tx_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) controller->can_dma = fsl_lpspi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) fsl_lpspi_dma_exit(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) fsl_lpspi->tx_buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fsl_lpspi->rx_buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fsl_lpspi->remain = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) reinit_completion(&fsl_lpspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) fsl_lpspi->slave_aborted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) fsl_lpspi_write_tx_fifo(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = fsl_lpspi_wait_for_completion(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) fsl_lpspi_reset(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int fsl_lpspi_transfer_one(struct spi_controller *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fsl_lpspi->is_first_byte = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = fsl_lpspi_setup_transfer(controller, spi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fsl_lpspi_set_cmd(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fsl_lpspi->is_first_byte = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (fsl_lpspi->usedma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = fsl_lpspi_pio_transfer(controller, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 temp_SR, temp_IER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct fsl_lpspi_data *fsl_lpspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) fsl_lpspi_intctrl(fsl_lpspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) fsl_lpspi_read_rx_fifo(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) fsl_lpspi_write_tx_fifo(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (temp_SR & SR_MBF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) complete(&fsl_lpspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int fsl_lpspi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct spi_controller *controller = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct fsl_lpspi_data *fsl_lpspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fsl_lpspi = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = clk_prepare_enable(fsl_lpspi->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) clk_disable_unprepare(fsl_lpspi->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int fsl_lpspi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct spi_controller *controller = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct fsl_lpspi_data *fsl_lpspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fsl_lpspi = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) clk_disable_unprepare(fsl_lpspi->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) clk_disable_unprepare(fsl_lpspi->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct device *dev = fsl_lpspi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int fsl_lpspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct fsl_lpspi_data *fsl_lpspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct spi_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) bool is_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) controller = spi_alloc_slave(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) sizeof(struct fsl_lpspi_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) controller = spi_alloc_master(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sizeof(struct fsl_lpspi_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) platform_set_drvdata(pdev, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) fsl_lpspi = spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) fsl_lpspi->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) fsl_lpspi->is_slave = is_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "fsl,spi-only-use-cs1-sel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) controller->transfer_one = fsl_lpspi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) controller->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) controller->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) controller->slave_abort = fsl_lpspi_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!fsl_lpspi->is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) controller->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) init_completion(&fsl_lpspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (IS_ERR(fsl_lpspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = PTR_ERR(fsl_lpspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) fsl_lpspi->base_phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_name(&pdev->dev), fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (IS_ERR(fsl_lpspi->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = PTR_ERR(fsl_lpspi->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (IS_ERR(fsl_lpspi->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = PTR_ERR(fsl_lpspi->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* enable the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = fsl_lpspi_init_rpm(fsl_lpspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto out_controller_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = pm_runtime_get_sync(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(fsl_lpspi->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto out_pm_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto out_pm_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = devm_spi_register_controller(&pdev->dev, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(&pdev->dev, "spi_register_controller error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto out_pm_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pm_runtime_mark_last_busy(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pm_runtime_put_autosuspend(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) out_pm_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pm_runtime_put_sync(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) pm_runtime_disable(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) out_controller_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) spi_controller_put(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int fsl_lpspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct spi_controller *controller = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct fsl_lpspi_data *fsl_lpspi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spi_controller_get_devdata(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pm_runtime_disable(fsl_lpspi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int __maybe_unused fsl_lpspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_err(dev, "Error in resume: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct dev_pm_ops fsl_lpspi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) fsl_lpspi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static struct platform_driver fsl_lpspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .of_match_table = fsl_lpspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .pm = &fsl_lpspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .probe = fsl_lpspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .remove = fsl_lpspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) module_platform_driver(fsl_lpspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MODULE_DESCRIPTION("LPSPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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