^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale SPI/eSPI controller driver library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Kumar Gala
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 Polycom, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * CPM SPI and QE buffer descriptors mode support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __SPI_FSL_LIB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __SPI_FSL_LIB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* SPI/eSPI Controller driver's private data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mpc8xxx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* rx & tx bufs from the spi_transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) const void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int subblock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct spi_pram __iomem *pram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef CONFIG_FSL_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct cpm_buf_desc __iomem *tx_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cpm_buf_desc __iomem *rx_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct spi_transfer *xfer_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* dma addresses for CPM transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dma_addr_t tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dma_addr_t rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool map_tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool map_rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dma_addr_t dma_dummy_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dma_addr_t dma_dummy_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* functions to deal with different sized buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32(*get_tx) (struct mpc8xxx_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned nsecs; /* (clock cycle time)/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 spibrg; /* SPIBRG input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 rx_shift; /* RX data reg shift when in qe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 tx_shift; /* TX data reg shift when in qe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if IS_ENABLED(CONFIG_SPI_FSL_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int native_chipselects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 max_bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int bits_per_word, int msb_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct spi_mpc8xxx_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* functions to deal with different sized buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 (*get_tx) (struct mpc8xxx_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 rx_shift; /* RX data reg shift when in qe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 tx_shift; /* TX data reg shift when in qe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 hw_mode; /* Holds HW mode register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iowrite32be(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ioread32be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mpc8xxx_spi_probe_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct fsl_spi_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __be32 __iomem *immr_spi_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct fsl_spi_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct spi_transfer *t, unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern const char *mpc8xxx_spi_strmode(unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern int mpc8xxx_spi_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* __SPI_FSL_LIB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags