^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale eSPI controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* eSPI Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ESPI_SPMODE 0x00 /* eSPI mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ESPI_SPIE 0x04 /* eSPI event register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ESPI_SPIM 0x08 /* eSPI mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ESPI_SPCOM 0x0c /* eSPI command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* eSPI Controller mode register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPMODE_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPMODE_LOOP BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPMODE_TXTHR(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPMODE_RXTHR(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* eSPI Controller CS mode register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CSMODE_CI_INACTIVEHIGH BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CSMODE_CP_BEGIN_EDGECLK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CSMODE_REV BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CSMODE_DIV16 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CSMODE_PM(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSMODE_POL_1 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CSMODE_LEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CSMODE_BEF(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CSMODE_AFT(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CSMODE_CG(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSL_ESPI_FIFO_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSL_ESPI_RXTHR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Default mode/csmode for eSPI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) | CSMODE_AFT(0) | CSMODE_CG(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* SPIE register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPIE_TXE BIT(15) /* TX FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPIE_DON BIT(14) /* TX done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPIE_RXT BIT(13) /* RX FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPIE_RXF BIT(12) /* RX FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPIE_TXT BIT(11) /* TX FIFO threshold*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPIE_RNE BIT(9) /* RX FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPIE_TNF BIT(8) /* TX FIFO not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* SPIM register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPIM_TXE BIT(15) /* TX FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPIM_DON BIT(14) /* TX done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPIM_RXT BIT(13) /* RX FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPIM_RXF BIT(12) /* RX FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPIM_TXT BIT(11) /* TX FIFO threshold*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPIM_RNE BIT(9) /* RX FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPIM_TNF BIT(8) /* TX FIFO not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SPCOM register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPCOM_CS(x) ((x) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPCOM_DO BIT(28) /* Dual output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPCOM_TO BIT(27) /* TX only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPCOM_RXSKIP(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPCOM_TRANLEN(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct fsl_espi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct list_head *m_transfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct spi_transfer *tx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct spi_transfer *rx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool swab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int rxskip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 spibrg; /* SPIBRG input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct fsl_espi_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 hw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ioread32be(espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ioread16be(espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ioread8(espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) iowrite32be(val, espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) iowrite16be(val, espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) iowrite8(val, espi->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int fsl_espi_check_message(struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct spi_transfer *t, *first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (m->frame_length > SPCOM_TRANLEN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(espi->dev, "message too long, size is %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) m->frame_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) first = list_first_entry(&m->transfers, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (first->bits_per_word != t->bits_per_word ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) first->speed_hz != t->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* ESPI supports MSB-first transfers for word size 8 / 16 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) first->bits_per_word != 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(espi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "MSB-first transfer not supported for wordsize %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) first->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct spi_transfer *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int i = 0, rxskip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * prerequisites for ESPI rxskip mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * - message has two transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * - first transfer is a write and second is a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * In addition the current low-level transfer mechanism requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * that the rxskip bytes fit into the TX FIFO. Else the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * the TX FIFO isn't re-filled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!t->tx_buf || t->rx_buf ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) t->len > FSL_ESPI_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rxskip = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else if (i == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (t->tx_buf || !t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return i == 2 ? rxskip : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 tx_fifo_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int tx_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const void *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* if events is zero transfer has not started and tx fifo is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tx_left = espi->tx_t->len - espi->tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tx_buf = espi->tx_t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (tx_left >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) fsl_espi_write_reg(espi, ESPI_SPITF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else if (espi->swab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fsl_espi_write_reg(espi, ESPI_SPITF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) swahb32p(tx_buf + espi->tx_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fsl_espi_write_reg(espi, ESPI_SPITF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *(u32 *)(tx_buf + espi->tx_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) espi->tx_pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tx_left -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tx_fifo_avail -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else if (tx_left >= 2 && tx_buf && espi->swab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fsl_espi_write_reg16(espi, ESPI_SPITF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) swab16p(tx_buf + espi->tx_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) espi->tx_pos += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tx_left -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tx_fifo_avail -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) fsl_espi_write_reg8(espi, ESPI_SPITF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *(u8 *)(tx_buf + espi->tx_pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) espi->tx_pos += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tx_left -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tx_fifo_avail -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!tx_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Last transfer finished, in rxskip mode only one is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (list_is_last(&espi->tx_t->transfer_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) espi->m_transfers) || espi->rxskip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) espi->tx_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) espi->tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* continue with next transfer if tx fifo is not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (tx_fifo_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 rx_fifo_avail = SPIE_RXCNT(events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int rx_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rx_left = espi->rx_t->len - espi->rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rx_buf = espi->rx_t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (rx_left >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (rx_buf && espi->swab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *(u32 *)(rx_buf + espi->rx_pos) = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) espi->rx_pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rx_left -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rx_fifo_avail -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else if (rx_left >= 2 && rx_buf && espi->swab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) espi->rx_pos += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rx_left -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) rx_fifo_avail -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *(u8 *)(rx_buf + espi->rx_pos) = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) espi->rx_pos += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rx_left -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) rx_fifo_avail -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!rx_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (list_is_last(&espi->rx_t->transfer_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) espi->m_transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) espi->rx_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) espi->rx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* continue with next transfer if rx fifo is not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (rx_fifo_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void fsl_espi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct fsl_espi *espi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct fsl_espi_cs *cs = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 hw_mode_old = cs->hw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* mask out bits we are going to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (pm > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cs->hw_mode |= CSMODE_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cs->hw_mode |= CSMODE_PM(pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* don't write the mode register if the mode doesn't change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (cs->hw_mode != hw_mode_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cs->hw_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct fsl_espi *espi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int rx_len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 mask, spcom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reinit_completion(&espi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) spcom = SPCOM_CS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spcom |= SPCOM_TRANLEN(t->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* configure RXSKIP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (espi->rxskip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spcom |= SPCOM_RXSKIP(espi->rxskip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rx_len = t->len - espi->rxskip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (t->rx_nbits == SPI_NBITS_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spcom |= SPCOM_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mask = SPIM_DON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (rx_len > FSL_ESPI_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mask |= SPIM_RXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fsl_espi_write_reg(espi, ESPI_SPIM, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Prevent filling the fifo from getting interrupted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spin_lock_irq(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fsl_espi_fill_tx_fifo(espi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_unlock_irq(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(espi->dev, "Transfer timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* disable rx ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) fsl_espi_write_reg(espi, ESPI_SPIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret == 0 ? -ETIMEDOUT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) espi->m_transfers = &m->transfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) espi->tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) espi->tx_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) espi->rx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) espi->rx_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) espi->rxskip = fsl_espi_check_rxskip_mode(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* In RXSKIP mode skip first transfer for reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (espi->rxskip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) fsl_espi_setup_transfer(spi, trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = fsl_espi_bufs(spi, trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spi_transfer_delay_exec(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int fsl_espi_do_one_msg(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int delay_usecs = 0, rx_nbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int delay_nsecs = 0, delay_nsecs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct spi_transfer *t, trans = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = fsl_espi_check_message(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (t->delay_usecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (t->delay_usecs > delay_usecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) delay_usecs = t->delay_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) delay_nsecs = delay_usecs * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) delay_nsecs1 = spi_delay_to_ns(&t->delay, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (delay_nsecs1 > delay_nsecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) delay_nsecs = delay_nsecs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (t->rx_nbits > rx_nbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rx_nbits = t->rx_nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) t = list_first_entry(&m->transfers, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) trans.len = m->frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) trans.speed_hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) trans.bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) trans.delay.value = delay_nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) trans.delay.unit = SPI_DELAY_UNIT_NSECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) trans.rx_nbits = rx_nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (trans.len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = fsl_espi_trans(m, &trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) m->actual_length = ret ? 0 : trans.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (m->status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) m->status = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int fsl_espi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct fsl_espi *espi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 loop_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct fsl_espi_cs *cs = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cs = kzalloc(sizeof(*cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spi_set_ctldata(spi, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) espi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pm_runtime_get_sync(espi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* mask out bits we are going to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) | CSMODE_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!(spi->mode & SPI_LSB_FIRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cs->hw_mode |= CSMODE_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Handle the loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) loop_mode &= ~SPMODE_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) loop_mode |= SPMODE_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) fsl_espi_setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pm_runtime_mark_last_busy(espi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_put_autosuspend(espi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void fsl_espi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct fsl_espi_cs *cs = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) spi_set_ctldata(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!espi->rx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fsl_espi_read_rx_fifo(espi, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!espi->tx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) fsl_espi_fill_tx_fifo(espi, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!espi->tx_done || !espi->rx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* we're done, but check for errors before returning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) events = fsl_espi_read_reg(espi, ESPI_SPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!(events & SPIE_DON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(espi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "Transfer done but SPIE_DON isn't set!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SPIE_RXCNT(events), SPIE_TXCNT(events));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) complete(&espi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct fsl_espi *espi = context_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 events, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) spin_lock(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Get interrupt events(tx/rx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) events = fsl_espi_read_reg(espi, ESPI_SPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mask = fsl_espi_read_reg(espi, ESPI_SPIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!(events & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) spin_unlock(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) fsl_espi_cpu_irq(espi, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Clear the events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fsl_espi_write_reg(espi, ESPI_SPIE, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) spin_unlock(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int fsl_espi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct fsl_espi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) regval &= ~SPMODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int fsl_espi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct fsl_espi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regval |= SPMODE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static size_t fsl_espi_max_message_size(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return SPCOM_TRANLEN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void fsl_espi_init_regs(struct device *dev, bool initial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct fsl_espi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct device_node *nc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 csmode, cs, prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* SPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fsl_espi_write_reg(espi, ESPI_SPIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Init eSPI CS mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) for_each_available_child_of_node(master->dev.of_node, nc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* get chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = of_property_read_u32(nc, "reg", &cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret || cs >= master->num_chipselect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) csmode = CSMODE_INIT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* check if CSBEF is set in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = of_property_read_u32(nc, "fsl,csbef", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) csmode &= ~(CSMODE_BEF(0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) csmode |= CSMODE_BEF(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* check if CSAFT is set in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = of_property_read_u32(nc, "fsl,csaft", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) csmode &= ~(CSMODE_AFT(0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) csmode |= CSMODE_AFT(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (initial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Enable SPI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int fsl_espi_probe(struct device *dev, struct resource *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int irq, unsigned int num_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct fsl_espi *espi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) master = spi_alloc_master(dev, sizeof(struct fsl_espi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_set_drvdata(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SPI_LSB_FIRST | SPI_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) master->setup = fsl_espi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) master->cleanup = fsl_espi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) master->transfer_one_message = fsl_espi_do_one_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) master->max_message_size = fsl_espi_max_message_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spin_lock_init(&espi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) espi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) espi->spibrg = fsl_get_sys_freq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (espi->spibrg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(dev, "Can't get sys frequency!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* determined by clock divider fields DIV16/PM in register SPMODEx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) init_completion(&espi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) espi->reg_base = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (IS_ERR(espi->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = PTR_ERR(espi->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Register for SPI Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) fsl_espi_init_regs(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto err_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_info(dev, "irq = %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) err_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pm_runtime_set_suspended(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) err_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int of_fsl_espi_get_chipselects(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int of_fsl_espi_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct resource mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int irq, num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (of_property_read_bool(np, "mode")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(dev, "mode property is not supported on ESPI!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) num_cs = of_fsl_espi_get_chipselects(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!num_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = of_address_to_resource(np, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return fsl_espi_probe(dev, &mem, irq, num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int of_fsl_espi_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pm_runtime_disable(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int of_fsl_espi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int of_fsl_espi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fsl_espi_init_regs(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const struct dev_pm_ops espi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fsl_espi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct of_device_id of_fsl_espi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { .compatible = "fsl,mpc8536-espi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct platform_driver fsl_espi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "fsl_espi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .of_match_table = of_fsl_espi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .pm = &espi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .probe = of_fsl_espi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .remove = of_fsl_espi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) module_platform_driver(fsl_espi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_AUTHOR("Mingkai Hu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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