^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Freescale DSPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // This file contains a driver for the Freescale DSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi-fsl-dspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRIVER_NAME "fsl-dspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPI_MCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPI_MCR_MASTER BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPI_MCR_PCSIS(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPI_MCR_CLR_TXF BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPI_MCR_CLR_RXF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPI_MCR_XSPI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_MCR_DIS_TXF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_MCR_DIS_RXF BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_MCR_HALT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_TCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_CTAR_CPOL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPI_CTAR_CPHA BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPI_CTAR_LSBFE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPI_CTAR_SCALE_BITS 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPI_CTAR0_SLAVE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_SR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPI_SR_TCFQF BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPI_SR_TFUF BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_SR_TFFF BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPI_SR_CMDTCF BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPI_SR_SPEF BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPI_SR_RFOF BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPI_SR_TFIWF BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPI_SR_RFDF BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPI_SR_CMDFFF BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPI_SR_CLEAR (SPI_SR_TCFQF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SPI_SR_TFUF | SPI_SR_TFFF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SPI_SR_CMDTCF | SPI_SR_SPEF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SPI_SR_RFOF | SPI_SR_TFIWF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SPI_SR_RFDF | SPI_SR_CMDFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPI_RSER_TFFFE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI_RSER_TFFFD BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPI_RSER_RFDFE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPI_RSER_RFDFD BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPI_RSER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPI_RSER_TCFQE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPI_RSER_CMDTCFE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPI_PUSHR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPI_PUSHR_CMD_CONT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPI_PUSHR_CMD_EOQ BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPI_PUSHR_CMD_CTCNT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPI_PUSHR_SLAVE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPI_POPR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPI_TXFR0 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPI_TXFR1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPI_TXFR2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPI_TXFR3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPI_RXFR0 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPI_RXFR1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPI_RXFR2 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPI_RXFR3 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPI_SREX 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 ctar_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum dspi_trans_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DSPI_DMA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct fsl_dspi_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum dspi_trans_mode trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 max_clock_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LS1021A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) LS1012A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LS1028A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) LS1043A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) LS1046A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LS2080A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) LS2085A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) LX2160A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MCF5441X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) VF610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct fsl_dspi_devtype_data devtype_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [VF610] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .trans_mode = DSPI_DMA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .max_clock_factor = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [LS1021A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Has A-011218 DMA erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [LS1012A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Has A-011218 DMA erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [LS1028A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [LS1043A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Has A-011218 DMA erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [LS1046A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Has A-011218 DMA erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [LS2080A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [LS2085A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [LX2160A] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .trans_mode = DSPI_XSPI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .fifo_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [MCF5441X] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .trans_mode = DSPI_DMA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .max_clock_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct fsl_dspi_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 *tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_addr_t tx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct completion cmd_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct dma_async_tx_descriptor *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 *rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dma_addr_t rx_dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct completion cmd_rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct dma_async_tx_descriptor *rx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct fsl_dspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct regmap *regmap_pushr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct spi_transfer *cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct spi_message *cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct chip_data *cur_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) size_t progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct fsl_dspi_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct completion xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct fsl_dspi_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int oper_bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int words_in_flight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * individually (in XSPI mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int pushr_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int pushr_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) switch (dspi->oper_word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *txdata = *(u8 *)dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *txdata = *(u16 *)dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *txdata = *(u32 *)dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dspi->tx += dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) switch (dspi->oper_word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *(u8 *)dspi->rx = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *(u16 *)dspi->rx = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *(u32 *)dspi->rx = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dspi->rx += dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *txdata = cpu_to_be32(*(u32 *)dspi->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dspi->tx += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *(u32 *)dspi->rx = be32_to_cpu(rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dspi->rx += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *txdata = cpu_to_be16(*(u16 *)dspi->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dspi->tx += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *(u16 *)dspi->rx = be16_to_cpu(rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dspi->rx += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 hi = *(u16 *)dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u16 lo = *(u16 *)(dspi->tx + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *txdata = (u32)hi << 16 | lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dspi->tx += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u16 hi = rxdata & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u16 lo = rxdata >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *(u16 *)dspi->rx = lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *(u16 *)(dspi->rx + 2) = hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dspi->rx += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Pop one word from the TX buffer for pushing into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * PUSHR register (TX FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static u32 dspi_pop_tx(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 txdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (dspi->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dspi->host_to_dev(dspi, &txdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dspi->len -= dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Prepare one TX FIFO entry (txdata plus cmd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (spi_controller_is_slave(dspi->ctlr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (dspi->len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cmd |= SPI_PUSHR_CMD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return cmd << 16 | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Push one word to the RX buffer from the POPR register (RX FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!dspi->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dspi->dev_to_host(dspi, rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void dspi_tx_dma_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct fsl_dspi *dspi = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct fsl_dspi_dma *dma = dspi->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) complete(&dma->cmd_tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void dspi_rx_dma_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct fsl_dspi *dspi = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct fsl_dspi_dma *dma = dspi->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (dspi->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (i = 0; i < dspi->words_in_flight; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) complete(&dma->cmd_rx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device *dev = &dspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct fsl_dspi_dma *dma = dspi->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < dspi->words_in_flight; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma->tx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dspi->words_in_flight *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!dma->tx_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(dev, "Not able to get desc for DMA xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dma->tx_desc->callback = dspi_tx_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dma->tx_desc->callback_param = dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(dev, "DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dma->rx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dspi->words_in_flight *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!dma->rx_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(dev, "Not able to get desc for DMA xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dma->rx_desc->callback = dspi_rx_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dma->rx_desc->callback_param = dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(dev, "DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) reinit_completion(&dspi->dma->cmd_rx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reinit_completion(&dspi->dma->cmd_tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_async_issue_pending(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_async_issue_pending(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (spi_controller_is_slave(dspi->ctlr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DMA_COMPLETION_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(dev, "DMA tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dmaengine_terminate_all(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dmaengine_terminate_all(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DMA_COMPLETION_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(dev, "DMA rx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dmaengine_terminate_all(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dmaengine_terminate_all(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void dspi_setup_accel(struct fsl_dspi *dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int dspi_dma_xfer(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct spi_message *message = dspi->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct device *dev = &dspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * dspi->len gets decremented by dspi_pop_tx_pushr in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * dspi_next_xfer_dma_submit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) while (dspi->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Figure out operational bits-per-word for this chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dspi_setup_accel(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dspi->words_in_flight = dspi->len / dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dspi->words_in_flight = dspi->devtype_data->fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) message->actual_length += dspi->words_in_flight *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = dspi_next_xfer_dma_submit(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev, "DMA transfer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int dma_bufsize = dspi->devtype_data->fifo_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device *dev = &dspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct fsl_dspi_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dma->chan_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (IS_ERR(dma->chan_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(dev, "rx dma channel not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = PTR_ERR(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dma->chan_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(dma->chan_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(dev, "tx dma channel not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = PTR_ERR(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto err_tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dma_bufsize, &dma->tx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!dma->tx_dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto err_tx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dma_bufsize, &dma->rx_dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!dma->rx_dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err_rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cfg.src_addr = phy_addr + SPI_POPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cfg.dst_addr = phy_addr + SPI_PUSHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cfg.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cfg.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cfg.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = dmaengine_slave_config(dma->chan_rx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev, "can't configure rx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cfg.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = dmaengine_slave_config(dma->chan_tx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(dev, "can't configure tx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto err_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dspi->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) init_completion(&dma->cmd_tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) init_completion(&dma->cmd_rx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) err_slave_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dma_free_coherent(dma->chan_rx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err_rx_dma_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dma_free_coherent(dma->chan_tx->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err_tx_dma_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err_tx_channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dma_release_channel(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) devm_kfree(dev, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dspi->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static void dspi_release_dma(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int dma_bufsize = dspi->devtype_data->fifo_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct fsl_dspi_dma *dma = dspi->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (dma->chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma->tx_dma_buf, dma->tx_dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (dma->chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dma->rx_dma_buf, dma->rx_dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dma_release_channel(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned long clkrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Valid baud rate pre-scaler values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int pbr_tbl[4] = {2, 3, 5, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int brs[16] = { 2, 4, 6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 16, 32, 64, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 256, 512, 1024, 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 4096, 8192, 16384, 32768 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int scale_needed, scale, minscale = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) scale_needed = clkrate / speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (clkrate % speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) scale_needed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (i = 0; i < ARRAY_SIZE(brs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) scale = brs[i] * pbr_tbl[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (scale >= scale_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (scale < minscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) minscale = scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *br = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *pbr = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (minscale == INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) speed_hz, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *pbr = ARRAY_SIZE(pbr_tbl) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) *br = ARRAY_SIZE(brs) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void ns_delay_scale(char *psc, char *sc, int delay_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned long clkrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int scale_needed, scale, minscale = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int pscale_tbl[4] = {1, 3, 5, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (remainder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) scale_needed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) scale = pscale_tbl[i] * (2 << j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (scale >= scale_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (scale < minscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) minscale = scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) *psc = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *sc = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (minscale == INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) delay_ns, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *psc = ARRAY_SIZE(pscale_tbl) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *sc = SPI_CTAR_SCALE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * The only time when the PCS doesn't need continuation after this word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * is when it's last. We need to look ahead, because we actually call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * dspi_pop_tx (the function that decrements dspi->len) _after_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * word is enough. If there's more to transmit than that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * dspi_xspi_write will know to split the FIFO writes in 2, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * generate a new PUSHR command with the final word that will have PCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * deasserted (not continued) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (dspi->len > dspi->oper_word_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) cmd |= SPI_PUSHR_CMD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int num_bytes = num_words * dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u16 tx_cmd = dspi->tx_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * If the PCS needs to de-assert (i.e. we're at the end of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * and cs_change does not want the PCS to stay on), then we need a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * PUSHR command, since this one (for the body of the buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * necessarily has the CONT bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * So send one word less during this go, to force a split and a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * with a single word next time, when CONT will be unset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tx_cmd |= SPI_PUSHR_CMD_EOQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Update CTARE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) regmap_write(dspi->regmap, SPI_CTARE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SPI_CTARE_DTCP(num_words));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * Write the CMD FIFO entry first, and then the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * corresponding TX FIFO entries (or one...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dspi_pushr_cmd_write(dspi, tx_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Fill TX FIFO with as many transfers as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) while (num_words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 data = dspi_pop_tx(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dspi_pushr_txdata_write(dspi, data & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (dspi->oper_bits_per_word > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dspi_pushr_txdata_write(dspi, data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static u32 dspi_popr_read(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 rxdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) regmap_read(dspi->regmap, SPI_POPR, &rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void dspi_fifo_read(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int num_fifo_entries = dspi->words_in_flight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Read one FIFO entry and push to rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) while (num_fifo_entries--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dspi_push_rx(dspi, dspi_popr_read(dspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static void dspi_setup_accel(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct spi_transfer *xfer = dspi->cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bool odd = !!(dspi->len & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* No accel for frames not multiple of 8 bits at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (xfer->bits_per_word % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto no_accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dspi->oper_bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dspi->oper_bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Start off with maximum supported by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dspi->oper_bits_per_word = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dspi->oper_bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * And go down only if the buffer can't be sent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * words this big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dspi->oper_bits_per_word /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } while (dspi->oper_bits_per_word > 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dspi->dev_to_host = dspi_8on32_dev_to_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dspi->host_to_dev = dspi_8on32_host_to_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dspi->dev_to_host = dspi_8on16_dev_to_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dspi->host_to_dev = dspi_8on16_host_to_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dspi->dev_to_host = dspi_16on32_dev_to_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dspi->host_to_dev = dspi_16on32_host_to_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) no_accel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dspi->dev_to_host = dspi_native_dev_to_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dspi->host_to_dev = dspi_native_host_to_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dspi->oper_bits_per_word = xfer->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Update CTAR here (code is common for XSPI and DMA modes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * We will update CTARE in the portion specific to XSPI, when we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * also know the preload value (DTCP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) regmap_write(dspi->regmap, SPI_CTAR(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dspi->cur_chip->ctar_val |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SPI_FRAME_BITS(dspi->oper_bits_per_word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void dspi_fifo_write(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int num_fifo_entries = dspi->devtype_data->fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct spi_transfer *xfer = dspi->cur_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct spi_message *msg = dspi->cur_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int num_words, num_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dspi_setup_accel(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (dspi->oper_word_size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) num_fifo_entries /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Integer division intentionally trims off odd (or non-multiple of 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * numbers of bytes at the end of the buffer, which will be sent next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * time using a smaller oper_word_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) num_words = dspi->len / dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (num_words > num_fifo_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) num_words = num_fifo_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Update total number of bytes that were transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) num_bytes = num_words * dspi->oper_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) msg->actual_length += num_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Update shared variable for use in the next interrupt (both in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * dspi_fifo_read and in dspi_fifo_write).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dspi->words_in_flight = num_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dspi_xspi_fifo_write(dspi, num_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Everything after this point is in a potential race with the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * interrupt, so we must never use dspi->words_in_flight again since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * might already be modified by the next dspi_fifo_write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dspi->progress, !dspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int dspi_rxtx(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dspi_fifo_read(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!dspi->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Success! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dspi_fifo_write(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int dspi_poll(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int tries = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 spi_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) regmap_read(dspi->regmap, SPI_SR, &spi_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) regmap_write(dspi->regmap, SPI_SR, spi_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (spi_sr & SPI_SR_CMDTCF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } while (--tries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!tries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return dspi_rxtx(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static irqreturn_t dspi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 spi_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) regmap_read(dspi->regmap, SPI_SR, &spi_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) regmap_write(dspi->regmap, SPI_SR, spi_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!(spi_sr & SPI_SR_CMDTCF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (dspi_rxtx(dspi) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) complete(&dspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int dspi_transfer_one_message(struct spi_controller *ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct spi_device *spi = message->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct spi_transfer *transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) message->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) list_for_each_entry(transfer, &message->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dspi->cur_transfer = transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dspi->cur_msg = message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dspi->cur_chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* Prepare command word for CMD FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SPI_PUSHR_CMD_PCS(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (list_is_last(&dspi->cur_transfer->transfer_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &dspi->cur_msg->transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Leave PCS activated after last transfer when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * cs_change is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (transfer->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* Keep PCS active between transfers in same message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * when cs_change is not set, and de-activate PCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * between transfers in the same message when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * cs_change is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!transfer->cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dspi->tx = transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dspi->rx = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dspi->len = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dspi->progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) regmap_update_bits(dspi->regmap, SPI_MCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dspi->progress, !dspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) status = dspi_dma_xfer(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dspi_fifo_write(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (dspi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) wait_for_completion(&dspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) reinit_completion(&dspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) status = dspi_poll(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } while (status == -EINPROGRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) spi_transfer_delay_exec(transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) message->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) spi_finalize_current_message(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int dspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 cs_sck_delay = 0, sck_cs_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct fsl_dspi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned char pasc = 0, asc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct chip_data *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Only alloc on first setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) chip = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pdata = dev_get_platdata(&dspi->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) &cs_sck_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) &sck_cs_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) cs_sck_delay = pdata->cs_sck_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sck_cs_delay = pdata->sck_cs_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) clkrate = clk_get_rate(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Set PCS to SCK delay scale values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Set After SCK delay scale values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) chip->ctar_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) chip->ctar_val |= SPI_CTAR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) chip->ctar_val |= SPI_CTAR_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!spi_controller_is_slave(dspi->ctlr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SPI_CTAR_CSSCK(cssck) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) SPI_CTAR_PASC(pasc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) SPI_CTAR_ASC(asc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SPI_CTAR_PBR(pbr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SPI_CTAR_BR(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) chip->ctar_val |= SPI_CTAR_LSBFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) spi_set_ctldata(spi, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static void dspi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) spi->controller->bus_num, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct of_device_id fsl_dspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .compatible = "fsl,vf610-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .data = &devtype_data[VF610],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .compatible = "fsl,ls1021a-v1.0-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .data = &devtype_data[LS1021A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .compatible = "fsl,ls1012a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .data = &devtype_data[LS1012A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .compatible = "fsl,ls1028a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .data = &devtype_data[LS1028A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .compatible = "fsl,ls1043a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .data = &devtype_data[LS1043A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .compatible = "fsl,ls1046a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .data = &devtype_data[LS1046A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .compatible = "fsl,ls2080a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .data = &devtype_data[LS2080A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .compatible = "fsl,ls2085a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .data = &devtype_data[LS2085A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .compatible = "fsl,lx2160a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .data = &devtype_data[LX2160A],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int dspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct fsl_dspi *dspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (dspi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) disable_irq(dspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) spi_controller_suspend(dspi->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) clk_disable_unprepare(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int dspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct fsl_dspi *dspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ret = clk_prepare_enable(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) spi_controller_resume(dspi->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (dspi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) enable_irq(dspi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const struct regmap_range dspi_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) regmap_reg_range(SPI_MCR, SPI_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) regmap_reg_range(SPI_SR, SPI_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct regmap_access_table dspi_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .yes_ranges = dspi_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct regmap_config dspi_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .max_register = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .volatile_table = &dspi_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const struct regmap_range dspi_xspi_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) regmap_reg_range(SPI_MCR, SPI_TCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) regmap_reg_range(SPI_SR, SPI_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) regmap_reg_range(SPI_SREX, SPI_SREX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const struct regmap_access_table dspi_xspi_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .yes_ranges = dspi_xspi_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static const struct regmap_config dspi_xspi_regmap_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .max_register = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .volatile_table = &dspi_xspi_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .name = "pushr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .max_register = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int dspi_init(struct fsl_dspi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) unsigned int mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Set idle states for all chip select signals to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mcr |= SPI_MCR_XSPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!spi_controller_is_slave(dspi->ctlr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mcr |= SPI_MCR_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) regmap_write(dspi->regmap, SPI_MCR, mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) switch (dspi->devtype_data->trans_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case DSPI_XSPI_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) case DSPI_DMA_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) regmap_write(dspi->regmap, SPI_RSER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SPI_RSER_TFFFE | SPI_RSER_TFFFD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SPI_RSER_RFDFE | SPI_RSER_RFDFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dspi->devtype_data->trans_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int dspi_slave_abort(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct fsl_dspi *dspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Terminate all pending DMA transactions for the SPI working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * in SLAVE mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dmaengine_terminate_sync(dspi->dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dmaengine_terminate_sync(dspi->dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* Clear the internal DSPI RX and TX FIFO buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) regmap_update_bits(dspi->regmap, SPI_MCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int dspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct fsl_dspi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int ret, cs_num, bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct fsl_dspi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) bool big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (!dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ctlr = spi_alloc_master(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (!ctlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spi_controller_set_devdata(ctlr, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) platform_set_drvdata(pdev, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dspi->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dspi->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ctlr->setup = dspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ctlr->transfer_one_message = dspi_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ctlr->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ctlr->cleanup = dspi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ctlr->slave_abort = dspi_slave_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ctlr->bus_num = pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Only Coldfire uses platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dspi->devtype_data = &devtype_data[MCF5441X];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) big_endian = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) of_property_read_u32(np, "bus-num", &bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ctlr->bus_num = bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (of_property_read_bool(np, "spi-slave"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ctlr->slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dspi->devtype_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (!dspi->devtype_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dev_err(&pdev->dev, "can't get devtype_data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) big_endian = of_device_is_big_endian(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dspi->pushr_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dspi->pushr_tx = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dspi->pushr_cmd = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dspi->pushr_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ret = PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) regmap_config = &dspi_xspi_regmap_config[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) regmap_config = &dspi_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (IS_ERR(dspi->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(&pdev->dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PTR_ERR(dspi->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = PTR_ERR(dspi->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dspi->regmap_pushr = devm_regmap_init_mmio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) &pdev->dev, base + SPI_PUSHR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) &dspi_xspi_regmap_config[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (IS_ERR(dspi->regmap_pushr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "failed to init pushr regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PTR_ERR(dspi->regmap_pushr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = PTR_ERR(dspi->regmap_pushr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dspi->clk = devm_clk_get(&pdev->dev, "dspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(dspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = PTR_ERR(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(&pdev->dev, "unable to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = clk_prepare_enable(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) goto out_ctlr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = dspi_init(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dspi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (dspi->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) "can't get platform irq, using poll mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dspi->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto poll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) init_completion(&dspi->xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) IRQF_SHARED, pdev->name, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) poll_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = dspi_request_dma(dspi, res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(&pdev->dev, "can't get dma channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ctlr->max_speed_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ctlr->ptp_sts_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = spi_register_controller(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto out_release_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) out_release_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dspi_release_dma(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (dspi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) free_irq(dspi->irq, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) out_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) clk_disable_unprepare(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) out_ctlr_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) spi_controller_put(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static int dspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct fsl_dspi *dspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Disconnect from the SPI framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) spi_unregister_controller(dspi->ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* Disable RX and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) regmap_update_bits(dspi->regmap, SPI_MCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* Stop Running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dspi_release_dma(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (dspi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) free_irq(dspi->irq, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) clk_disable_unprepare(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static void dspi_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) dspi_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static struct platform_driver fsl_dspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .driver.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .driver.of_match_table = fsl_dspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .driver.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .driver.pm = &dspi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .probe = dspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .remove = dspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .shutdown = dspi_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) module_platform_driver(fsl_dspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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