^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Cirrus Logic EP93xx SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Mika Westerberg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Explicit FIFO handling code was inspired by amba-pl022 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * For more information about the SPI controller see documentation on Cirrus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Logic web site:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * https://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/dma-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/spi-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSPCR0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SSPCR0_SPO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SSPCR0_SPH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SSPCR0_SCR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SSPCR1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SSPCR1_RIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SSPCR1_TIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SSPCR1_RORIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SSPCR1_LBM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSPCR1_SSE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SSPCR1_MS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SSPCR1_SOD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SSPDR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SSPSR 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SSPSR_TFE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSPSR_TNF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSPSR_RNE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SSPSR_RFF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSPSR_BSY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SSPCPSR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SSPIIR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SSPIIR_RIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SSPIIR_TIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SSPIIR_RORIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SSPICR SSPIIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* timeout in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPI_TIMEOUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* maximum depth of RX/TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPI_FIFO_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * struct ep93xx_spi - EP93xx SPI controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @clk: clock for the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @mmio: pointer to ioremap()'d registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @sspdr_phys: physical address of the SSPDR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @tx: current byte in transfer to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @rx: current byte in transfer to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * frame decreases this level and sending one frame increases it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @dma_rx: RX DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @dma_tx: TX DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @dma_rx_data: RX parameters passed to the DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @dma_tx_data: TX parameters passed to the DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @rx_sgt: sg table for RX transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @tx_sgt: sg table for TX transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ep93xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long sspdr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) size_t tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) size_t rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) size_t fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ep93xx_dma_data dma_rx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ep93xx_dma_data dma_tx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct sg_table rx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sg_table tx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void *zeropage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* converts bits per word to CR0.DSS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define bits_per_word_to_dss(bpw) ((bpw) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @master: SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @rate: desired SPI output clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @div_scr: pointer to return the scr divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ep93xx_spi_calc_divisors(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 rate, u8 *div_cpsr, u8 *div_scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long spi_clk_rate = clk_get_rate(espi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int cpsr, scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Make sure that max value is between values supported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Calculate divisors so that we can get speed according the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * following formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * rate = spi_clock_rate / (cpsr * (1 + scr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * cpsr must be even number and starts from 2, scr can be any number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * between 0 and 255.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (cpsr = 2; cpsr <= 254; cpsr += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (scr = 0; scr <= 255; scr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *div_scr = (u8)scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *div_cpsr = (u8)cpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int ep93xx_spi_chip_setup(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 div_cpsr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 div_scr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &div_cpsr, &div_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cr0 = div_scr << SSPCR0_SCR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cr0 |= SSPCR0_SPO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cr0 |= SSPCR0_SPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cr0 |= dss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spi->mode, div_cpsr, div_scr, dss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(div_cpsr, espi->mmio + SSPCPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(cr0, espi->mmio + SSPCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void ep93xx_do_write(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct spi_transfer *xfer = master->cur_msg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (xfer->bits_per_word > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = ((u16 *)xfer->tx_buf)[espi->tx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) espi->tx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = ((u8 *)xfer->tx_buf)[espi->tx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) espi->tx += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(val, espi->mmio + SSPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void ep93xx_do_read(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct spi_transfer *xfer = master->cur_msg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = readl(espi->mmio + SSPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (xfer->bits_per_word > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ((u16 *)xfer->rx_buf)[espi->rx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) espi->rx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ((u8 *)xfer->rx_buf)[espi->rx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) espi->rx += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * ep93xx_spi_read_write() - perform next RX/TX transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @master: SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * called several times, the whole transfer will be completed. Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * When this function is finished, RX FIFO should be empty and TX FIFO should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ep93xx_spi_read_write(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct spi_transfer *xfer = master->cur_msg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* read as long as RX FIFO has frames in it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ep93xx_do_read(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) espi->fifo_level--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* write as long as TX FIFO has room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ep93xx_do_write(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) espi->fifo_level++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (espi->rx == xfer->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static enum dma_transfer_direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case DMA_TO_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case DMA_FROM_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return DMA_TRANS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * ep93xx_spi_dma_prepare() - prepares a DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @master: SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @dir: DMA transfer direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Function configures the DMA, maps the buffer and prepares the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ep93xx_spi_dma_prepare(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct spi_transfer *xfer = master->cur_msg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct dma_async_tx_descriptor *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct dma_slave_config conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const void *buf, *pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) size_t len = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int i, ret, nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (xfer->bits_per_word > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) memset(&conf, 0, sizeof(conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) conf.direction = ep93xx_dma_data_to_trans_dir(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) chan = espi->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) buf = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sgt = &espi->rx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) conf.src_addr = espi->sspdr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) conf.src_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) chan = espi->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) buf = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sgt = &espi->tx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) conf.dst_addr = espi->sspdr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) conf.dst_addr_width = buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = dmaengine_slave_config(chan, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * We need to split the transfer into PAGE_SIZE'd chunks. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * because we are using @espi->zeropage to provide a zero RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * for the TX transfers and we have only allocated one page for that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * For performance reasons we allocate a new sg_table only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * needed. Otherwise we will re-use the current one. Eventually the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * last sg_table is released in ep93xx_spi_release_dma().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) nents = DIV_ROUND_UP(len, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (nents != sgt->nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sg_free_table(sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pbuf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for_each_sg(sgt->sgl, sg, sgt->nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) size_t bytes = min_t(size_t, len, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sg_set_page(sg, virt_to_page(pbuf), bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) offset_in_page(pbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sg_set_page(sg, virt_to_page(espi->zeropage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pbuf += bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) len -= bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (WARN_ON(len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_warn(&master->dev, "len = %zu expected 0!\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!txd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * ep93xx_spi_dma_finish() - finishes with a DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * @master: SPI master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @dir: DMA transfer direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Function finishes with the DMA transfer. After this, the DMA buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * unmapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void ep93xx_spi_dma_finish(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chan = espi->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sgt = &espi->rx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) chan = espi->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sgt = &espi->tx_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void ep93xx_spi_dma_callback(void *callback_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct spi_master *master = callback_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ep93xx_spi_dma_finish(master, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int ep93xx_spi_dma_transfer(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct dma_async_tx_descriptor *rxd, *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rxd = ep93xx_spi_dma_prepare(master, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (IS_ERR(rxd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PTR_ERR(rxd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) txd = ep93xx_spi_dma_prepare(master, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(txd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return PTR_ERR(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* We are ready when RX is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rxd->callback = ep93xx_spi_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rxd->callback_param = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Now submit both descriptors and start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dmaengine_submit(rxd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dmaengine_submit(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_async_issue_pending(espi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dma_async_issue_pending(espi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* signal that we need to wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * If we got ROR (receive overrun) interrupt we know that something is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * wrong. Just abort the message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* clear the overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel(0, espi->mmio + SSPICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_warn(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "receive overrun, aborting the message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) master->cur_msg->status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Interrupt is either RX (RIS) or TX (TIS). For both cases we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * simply execute next data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ep93xx_spi_read_write(master)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * In normal case, there still is some processing left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * for current transfer. Let's wait for the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * interrupt then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Current transfer is finished, either with error or with success. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * any case we disable interrupts and notify the worker to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * any post-processing of the message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = readl(espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) writel(val, espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int ep93xx_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = ep93xx_spi_chip_setup(master, spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(&master->dev, "failed to setup chip for transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) master->cur_msg->state = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) espi->rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) espi->tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * There is no point of setting up DMA for the transfers which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * fit into the FIFO and can be transferred with a single interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * So in these cases we will be using PIO and don't bother for DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ep93xx_spi_dma_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Using PIO so prime the TX FIFO and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ep93xx_spi_read_write(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val = readl(espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(val, espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* signal that we need to wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int ep93xx_spi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Just to be sure: flush any data from RX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_warn(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "timeout while flushing RX FIFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) readl(espi->mmio + SSPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * We explicitly handle FIFO level. This way we don't have to check TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) espi->fifo_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int ep93xx_spi_prepare_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = clk_enable(espi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = readl(espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val |= SSPCR1_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(val, espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int ep93xx_spi_unprepare_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) val = readl(espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val &= ~SSPCR1_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) writel(val, espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) clk_disable(espi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ep93xx_dma_chan_is_m2p(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) chan->private = filter_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!espi->zeropage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) espi->dma_rx_data.port = EP93XX_DMA_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) espi->dma_rx_data.name = "ep93xx-spi-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &espi->dma_rx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!espi->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto fail_free_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) espi->dma_tx_data.port = EP93XX_DMA_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) espi->dma_tx_data.name = "ep93xx-spi-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &espi->dma_tx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!espi->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto fail_release_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fail_release_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dma_release_channel(espi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) espi->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fail_free_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) free_page((unsigned long)espi->zeropage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (espi->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dma_release_channel(espi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sg_free_table(&espi->rx_sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (espi->dma_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dma_release_channel(espi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sg_free_table(&espi->tx_sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (espi->zeropage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) free_page((unsigned long)espi->zeropage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int ep93xx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct ep93xx_spi_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ep93xx_spi *espi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) info = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&pdev->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev, "unable to get iomem resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) master = spi_alloc_master(&pdev->dev, sizeof(*espi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) master->prepare_message = ep93xx_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) master->transfer_one = ep93xx_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * The SPI core will count the number of GPIO descriptors to figure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * out the number of chip selects available on the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) master->num_chipselect = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) espi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (IS_ERR(espi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&pdev->dev, "unable to get spi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) error = PTR_ERR(espi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto fail_release_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Calculate maximum and minimum supported clock rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * for the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) master->max_speed_hz = clk_get_rate(espi->clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) espi->sspdr_phys = res->start + SSPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) espi->mmio = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (IS_ERR(espi->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) error = PTR_ERR(espi->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto fail_release_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0, "ep93xx-spi", master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_err(&pdev->dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto fail_release_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (info->use_dma && ep93xx_spi_setup_dma(espi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* make sure that the hardware is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel(0, espi->mmio + SSPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) error = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(&pdev->dev, "failed to register SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto fail_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (unsigned long)res->start, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fail_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ep93xx_spi_release_dma(espi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) fail_release_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int ep93xx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct ep93xx_spi *espi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ep93xx_spi_release_dma(espi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct platform_driver ep93xx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .name = "ep93xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .probe = ep93xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .remove = ep93xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) module_platform_driver(ep93xx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MODULE_DESCRIPTION("EP93xx SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MODULE_ALIAS("platform:ep93xx-spi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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