Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_data/efm32-spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DRIVER_NAME "efm32-spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MASK_VAL(mask, val)		((val << __ffs(mask)) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_CTRL_SYNC			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_CTRL_CLKPOL			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_CTRL_CLKPHA			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_CTRL_MSBF			0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_CTRL_TXBIL			0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_FRAME		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_FRAME_DATABITS__MASK	0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_FRAME_DATABITS(n)		((n) - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_CMD			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_CMD_RXEN			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_CMD_RXDIS			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_CMD_TXEN			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_CMD_TXDIS			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_CMD_MASTEREN		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_STATUS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_STATUS_TXENS		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_STATUS_TXC			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_STATUS_TXBL			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_STATUS_RXDATAV		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_CLKDIV		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG_RXDATAX		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_RXDATAX_RXDATA__MASK	0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_RXDATAX_PERR		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG_RXDATAX_FERR		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG_TXDATA		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define REG_IF		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG_IF_TXBL			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_IF_RXDATAV			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_IFS		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_IFC		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_IEN		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define REG_ROUTE		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_ROUTE_RXPEN			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_ROUTE_TXPEN			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_ROUTE_CLKPEN		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_ROUTE_LOCATION__MASK	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_ROUTE_LOCATION(n)		MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct efm32_spi_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int rxirq, txirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct efm32_spi_pdata pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* irq data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned tx_len, rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ddata_to_dev(ddata)	(&(ddata->bitbang.master->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define efm32_spi_vdbg(ddata, format, arg...)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	dev_vdbg(ddata_to_dev(ddata), format, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		u32 value, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	writel_relaxed(value, ddata->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return readl_relaxed(ddata->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int efm32_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned speed = t->speed_hz ?: spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned long clkfreq = clk_get_rate(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			(spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			(spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	efm32_spi_write32(ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			REG_FRAME_DATABITS(bpw), REG_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (2 * speed >= clkfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		clkdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (clkdiv > (1U << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (ddata->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		val = *ddata->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		ddata->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ddata->tx_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	efm32_spi_write32(ddata, val, REG_TXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (ddata->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		*ddata->rx_buf = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ddata->rx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ddata->rx_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	while (ddata->tx_len &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			ddata->tx_len + 2 > ddata->rx_len &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		efm32_spi_tx_u8(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	spin_lock_irq(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (ddata->tx_buf || ddata->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ddata->tx_buf = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ddata->rx_buf = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ddata->tx_len = ddata->rx_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		t->len * DIV_ROUND_UP(t->bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	efm32_spi_filltx(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	reinit_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	spin_unlock_irq(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	wait_for_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	spin_lock_irq(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = t->len - max(ddata->tx_len, ddata->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	efm32_spi_write32(ddata, 0, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ddata->tx_buf = ddata->rx_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	spin_unlock_irq(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static irqreturn_t efm32_spi_rxirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct efm32_spi_ddata *ddata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	spin_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	while (ddata->rx_len > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			efm32_spi_read32(ddata, REG_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			REG_STATUS_RXDATAV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		efm32_spi_rx_u8(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!ddata->rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		u32 ien = efm32_spi_read32(ddata, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		ien &= ~REG_IF_RXDATAV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		efm32_spi_write32(ddata, ien, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	spin_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static irqreturn_t efm32_spi_txirq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct efm32_spi_ddata *ddata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	efm32_spi_vdbg(ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			"%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			__func__, ddata->tx_len, ddata->rx_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			efm32_spi_read32(ddata, REG_IF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			efm32_spi_read32(ddata, REG_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	spin_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	efm32_spi_filltx(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			__func__, ddata->tx_len, ddata->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (!ddata->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		u32 ien = efm32_spi_read32(ddata, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ien &= ~REG_IF_TXBL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		efm32_spi_write32(ddata, ien, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		efm32_spi_vdbg(ddata, "disable TXBL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	spin_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void efm32_spi_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		struct spi_master *master, struct efm32_spi_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u32 location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ret = of_property_read_u32(np, "energymicro,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		/* fall back to wrongly namespaced property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		ret = of_property_read_u32(np, "efm32,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		/* fall back to old and (wrongly) generic property "location" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = of_property_read_u32(np, "location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dev_dbg(&pdev->dev, "using location %u\n", location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		/* default to location configured in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		location = efm32_spi_get_configured_location(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		dev_info(&pdev->dev, "fall back to location %u\n", location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ddata->pdata.location = location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int efm32_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct efm32_spi_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	master = spi_alloc_master(&pdev->dev, sizeof(*ddata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				"failed to allocate spi master controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ddata = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ddata->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	spin_lock_init(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	init_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ddata->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (IS_ERR(ddata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		ret = PTR_ERR(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		dev_err(&pdev->dev, "failed to determine base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (resource_size(res) < 0x60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		dev_err(&pdev->dev, "memory resource too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ddata->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (IS_ERR(ddata->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		ret = PTR_ERR(ddata->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ddata->rxirq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ret = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		ret = ddata->rxirq + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ddata->txirq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ret = clk_prepare_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	efm32_spi_probe_dt(pdev, master, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	efm32_spi_write32(ddata, 0, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			REG_ROUTE_CLKPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			0, DRIVER_NAME " rx", ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ret = request_irq(ddata->txirq, efm32_spi_txirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			0, DRIVER_NAME " tx", ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		goto err_free_rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ret = spi_bitbang_start(&ddata->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		free_irq(ddata->txirq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) err_free_rx_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		free_irq(ddata->rxirq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int efm32_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	spi_bitbang_stop(&ddata->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	efm32_spi_write32(ddata, 0, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	free_irq(ddata->txirq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	free_irq(ddata->rxirq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct of_device_id efm32_spi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.compatible = "energymicro,efm32-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		/* doesn't follow the "vendor,device" scheme, don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.compatible = "efm32,spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct platform_driver efm32_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.probe = efm32_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.remove = efm32_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.of_match_table = efm32_spi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) module_platform_driver(efm32_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_DESCRIPTION("EFM32 SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_ALIAS("platform:" DRIVER_NAME);