Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef DW_SPI_HEADER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define DW_SPI_HEADER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DW_SPI_CTRLR0			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DW_SPI_CTRLR1			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DW_SPI_SSIENR			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DW_SPI_MWCR			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DW_SPI_SER			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DW_SPI_BAUDR			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DW_SPI_TXFTLR			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DW_SPI_RXFTLR			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DW_SPI_TXFLR			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DW_SPI_RXFLR			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DW_SPI_SR			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DW_SPI_IMR			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DW_SPI_ISR			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DW_SPI_RISR			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DW_SPI_TXOICR			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DW_SPI_RXOICR			0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DW_SPI_RXUICR			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DW_SPI_MSTICR			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DW_SPI_ICR			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DW_SPI_DMACR			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DW_SPI_DMATDLR			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DW_SPI_DMARDLR			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DW_SPI_IDR			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DW_SPI_VERSION			0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DW_SPI_DR			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DW_SPI_RX_SAMPLE_DLY		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DW_SPI_CS_OVERRIDE		0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Bit fields in CTRLR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SPI_DFS_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SPI_FRF_OFFSET			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SPI_FRF_SPI			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SPI_FRF_SSP			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SPI_FRF_MICROWIRE		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SPI_FRF_RESV			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SPI_MODE_OFFSET			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SPI_SCPH_OFFSET			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SPI_SCOL_OFFSET			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SPI_TMOD_OFFSET			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	SPI_TMOD_TR			0x0		/* xmit & recv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SPI_TMOD_TO			0x1		/* xmit only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SPI_TMOD_RO			0x2		/* recv only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SPI_SLVOE_OFFSET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SPI_SRL_OFFSET			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SPI_CFS_OFFSET			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DWC_SSI_CTRLR0_SRL_OFFSET	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DWC_SSI_CTRLR0_TMOD_OFFSET	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DWC_SSI_CTRLR0_TMOD_MASK	GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DWC_SSI_CTRLR0_SCPOL_OFFSET	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DWC_SSI_CTRLR0_SCPH_OFFSET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DWC_SSI_CTRLR0_FRF_OFFSET	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DWC_SSI_CTRLR0_DFS_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * For Keem Bay, CTRLR0[31] is used to select controller mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * 0: SSI is slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * 1: SSI is master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DWC_SSI_CTRLR0_KEEMBAY_MST	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* Bit fields in CTRLR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SPI_NDF_MASK			GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Bit fields in SR, 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SR_MASK				0x7f		/* cover 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SR_BUSY				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SR_TF_NOT_FULL			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SR_TF_EMPT			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SR_RF_NOT_EMPT			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SR_RF_FULL			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SR_TX_ERR			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SR_DCOL				(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* Bit fields in ISR, IMR, RISR, 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SPI_INT_TXEI			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SPI_INT_TXOI			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SPI_INT_RXUI			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SPI_INT_RXOI			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPI_INT_RXFI			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPI_INT_MSTI			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Bit fields in DMACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPI_DMA_RDMAE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPI_DMA_TDMAE			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPI_WAIT_RETRIES		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPI_BUF_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	(sizeof_field(struct spi_mem_op, cmd.opcode) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 sizeof_field(struct spi_mem_op, addr.val) + 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPI_GET_BYTE(_val, _idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum dw_ssi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	SSI_MOTO_SPI = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	SSI_TI_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	SSI_NS_MICROWIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* DW SPI capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DW_SPI_CAP_KEEMBAY_MST		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DW_SPI_CAP_DWC_SSI		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Slave spi_transfer/spi_mem_op related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct dw_spi_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 tmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u8 dfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 ndf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dw_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct dw_spi_dma_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int (*dma_init)(struct device *dev, struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	void (*dma_exit)(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			struct spi_transfer *xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	void (*dma_stop)(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct dw_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct spi_controller	*master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned long		paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32			fifo_len;	/* depth of the FIFO buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32			max_mem_freq;	/* max mem-ops bus freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32			max_freq;	/* max bus freq supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32			caps;		/* DW SPI capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32			reg_io_width;	/* DR I/O width in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u16			bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u16			num_cs;		/* supported slave numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	void (*set_cs)(struct spi_device *spi, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Current message transfer state info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	void			*tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned int		tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	void			*rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int		rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8			buf[SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int			dma_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8			n_bytes;	/* current is a 1/2 bytes op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32			current_freq;	/* frequency in hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32			cur_rx_sample_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32			def_rx_sample_dly_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Custom memory operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct spi_controller_mem_ops mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* DMA info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct dma_chan		*txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32			txburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct dma_chan		*rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32			rxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32			dma_sg_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned long		dma_chan_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	dma_addr_t		dma_addr; /* phy address of the Data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	const struct dw_spi_dma_ops *dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct completion	dma_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct debugfs_regset32 regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return __raw_readl(dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	__raw_writel(val, dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	switch (dws->reg_io_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return readw_relaxed(dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return readl_relaxed(dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	switch (dws->reg_io_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		writew_relaxed(val, dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		writel_relaxed(val, dws->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void spi_enable_chip(struct dw_spi *dws, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline void spi_set_clk(struct dw_spi *dws, u16 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dw_writel(dws, DW_SPI_BAUDR, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Disable IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u32 new_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	dw_writel(dws, DW_SPI_IMR, new_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Enable IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 new_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dw_writel(dws, DW_SPI_IMR, new_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * This disables the SPI controller, interrupts, clears the interrupts status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * and CS, then re-enables the controller back. Transmit and receive FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * buffers are cleared when the device is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void spi_reset_chip(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	spi_enable_chip(dws, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	spi_mask_intr(dws, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	dw_readl(dws, DW_SPI_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dw_writel(dws, DW_SPI_SER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	spi_enable_chip(dws, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline void spi_shutdown_chip(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	spi_enable_chip(dws, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	spi_set_clk(dws, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				 struct dw_spi_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern void dw_spi_remove_host(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern int dw_spi_suspend_host(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) extern int dw_spi_resume_host(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef CONFIG_SPI_DW_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* !CONFIG_SPI_DW_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif /* DW_SPI_HEADER_H */