Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Memory-mapped interface driver for DW SPI Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2010, Octasic semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "spi-dw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DRIVER_NAME "dw_spi_mmio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct dw_spi_mmio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct dw_spi  dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct clk     *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct clk     *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	void           *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OCELOT_IF_SI_OWNER_OFFSET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define JAGUAR2_IF_SI_OWNER_OFFSET		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MSCC_IF_SI_OWNER_MASK			GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MSCC_IF_SI_OWNER_SISL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MSCC_IF_SI_OWNER_SIBM			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MSCC_IF_SI_OWNER_SIMC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MSCC_SPI_MST_SW_MODE			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SPARX5_FORCE_ENA			0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SPARX5_FORCE_VAL			0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct dw_spi_mscc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regmap       *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem        *spi_mst; /* Not sparx5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * The Designware SPI controller (referred to as master in the documentation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * automatically deasserts chip select when the tx fifo is empty. The chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * selects then needs to be either driven as GPIOs or, for the first 4 using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * the SPI boot controller registers. the final chip select is an OR gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * between the Designware SPI controller and the SPI boot controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct dw_spi *dws = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (cs < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	dw_spi_set_cs(spi, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int dw_spi_mscc_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			    struct dw_spi_mmio *dwsmmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			    const char *cpu_syscon, u32 if_si_owner_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct dw_spi_mscc *dwsmscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (!dwsmscc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (IS_ERR(dwsmscc->spi_mst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_err(&pdev->dev, "SPI_MST region map failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return PTR_ERR(dwsmscc->spi_mst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (IS_ERR(dwsmscc->syscon))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return PTR_ERR(dwsmscc->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* Deassert all CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* Select the owner of the SI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			   MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			   MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	dwsmmio->priv = dwsmscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				   struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				OCELOT_IF_SI_OWNER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				    struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				JAGUAR2_IF_SI_OWNER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * The Designware SPI controller (referred to as master in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * documentation) automatically deasserts chip select when the tx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * is empty. The chip selects then needs to be driven by a CS override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * register. enable is an active low signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct dw_spi *dws = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8 cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		/* CS override drive enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		/* Now set CSx enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/* Allow settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		usleep_range(1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		/* CS value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		/* Allow settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		usleep_range(1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		/* CS override drive disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dw_spi_set_cs(spi, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				   struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	const char *syscon_name = "microchip,sparx5-cpu-syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct dw_spi_mscc *dwsmscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!IS_ENABLED(CONFIG_SPI_MUX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!dwsmscc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	dwsmscc->syscon =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		syscon_regmap_lookup_by_compatible(syscon_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (IS_ERR(dwsmscc->syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(dev, "No syscon map %s\n", syscon_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return PTR_ERR(dwsmscc->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	dwsmmio->priv = dwsmscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int dw_spi_alpine_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			      struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int dw_spi_dw_apb_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			      struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	dw_spi_dma_setup_generic(&dwsmmio->dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			       struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dwsmmio->dws.caps = DW_SPI_CAP_DWC_SSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	dw_spi_dma_setup_generic(&dwsmmio->dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int dw_spi_keembay_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			       struct dw_spi_mmio *dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST | DW_SPI_CAP_DWC_SSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int dw_spi_mmio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int (*init_func)(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 struct dw_spi_mmio *dwsmmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct dw_spi_mmio *dwsmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct dw_spi *dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (!dwsmmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dws = &dwsmmio->dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Get basic io resource and map it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (IS_ERR(dws->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return PTR_ERR(dws->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dws->paddr = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dws->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (dws->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return dws->irq; /* -ENXIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (IS_ERR(dwsmmio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return PTR_ERR(dwsmmio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = clk_prepare_enable(dwsmmio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* Optional clock needed to access the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (IS_ERR(dwsmmio->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		ret = PTR_ERR(dwsmmio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = clk_prepare_enable(dwsmmio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/* find an optional reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (IS_ERR(dwsmmio->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ret = PTR_ERR(dwsmmio->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	reset_control_deassert(dwsmmio->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	dws->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	dws->max_freq = clk_get_rate(dwsmmio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	num_cs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	dws->num_cs = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	init_func = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (init_func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		ret = init_func(pdev, dwsmmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ret = dw_spi_add_host(&pdev->dev, dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	platform_set_drvdata(pdev, dwsmmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	clk_disable_unprepare(dwsmmio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	clk_disable_unprepare(dwsmmio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	reset_control_assert(dwsmmio->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int dw_spi_mmio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	dw_spi_remove_host(&dwsmmio->dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	clk_disable_unprepare(dwsmmio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	clk_disable_unprepare(dwsmmio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	reset_control_assert(dwsmmio->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct of_device_id dw_spi_mmio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ /* end of table */}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct platform_driver dw_spi_mmio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.probe		= dw_spi_mmio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.remove		= dw_spi_mmio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.of_match_table = dw_spi_mmio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) module_platform_driver(dw_spi_mmio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_LICENSE("GPL v2");