^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Special handling for DW DMA core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009, 2014 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_data/dma-dw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "spi-dw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RX_BUSY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RX_BURST_LEVEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TX_BUSY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TX_BURST_LEVEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct dw_dma_slave *s = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (s->dma_dev != chan->device->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) chan->private = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct dma_slave_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 max_burst, def_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) def_burst = dws->fifo_len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = dma_get_slave_caps(dws->rxchan, &caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!ret && caps.max_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) max_burst = caps.max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) max_burst = RX_BURST_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dws->rxburst = min(max_burst, def_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = dma_get_slave_caps(dws->txchan, &caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!ret && caps.max_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) max_burst = caps.max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) max_burst = TX_BURST_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Having a Rx DMA channel serviced with higher priority than a Tx DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * channel might not be enough to provide a well balanced DMA-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * SPI transfer interface. There might still be moments when the Tx DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * channel is occasionally handled faster than the Rx DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * That in its turn will eventually cause the SPI Rx FIFO overflow if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * cleared by the Rx DMA channel. In order to fix the problem the Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * DMA activity is intentionally slowed down by limiting the SPI Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * FIFO depth with a value twice bigger than the Tx burst length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dws->txburst = min(max_burst, def_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void dw_spi_dma_sg_burst_init(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dma_slave_caps tx = {0}, rx = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dma_get_slave_caps(dws->txchan, &tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dma_get_slave_caps(dws->rxchan, &rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else if (tx.max_sg_burst > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dws->dma_sg_burst = tx.max_sg_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else if (rx.max_sg_burst > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dws->dma_sg_burst = rx.max_sg_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dws->dma_sg_burst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pci_dev *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Get pci device for DMA controller, currently it could only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * be the DMA controller of Medfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!dma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 1. Init rx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rx->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!dws->rxchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 2. Init tx channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tx->dma_dev = &dma_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!dws->txchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto free_rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dws->master->dma_rx = dws->rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dws->master->dma_tx = dws->txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) init_completion(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dw_spi_dma_maxburst_init(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dw_spi_dma_sg_burst_init(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) free_rxchan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dma_release_channel(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dws->rxchan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dws->rxchan = dma_request_slave_channel(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!dws->rxchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dws->txchan = dma_request_slave_channel(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!dws->txchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dma_release_channel(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dws->rxchan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dws->master->dma_rx = dws->rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dws->master->dma_tx = dws->txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) init_completion(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dw_spi_dma_maxburst_init(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dw_spi_dma_sg_burst_init(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void dw_spi_dma_exit(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (dws->txchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dmaengine_terminate_sync(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dma_release_channel(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (dws->rxchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dmaengine_terminate_sync(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dma_release_channel(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dw_spi_check_status(dws, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) complete(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static bool dw_spi_can_dma(struct spi_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct dw_spi *dws = spi_controller_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return xfer->len > dws->fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (n_bytes == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else if (n_bytes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return DMA_SLAVE_BUSWIDTH_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long long ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ms = len * MSEC_PER_SEC * BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) do_div(ms, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ms += ms + 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ms > UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ms = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ms = wait_for_completion_timeout(&dws->dma_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msecs_to_jiffies(ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ms == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(&dws->master->cur_msg->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "DMA transaction timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int retry = SPI_WAIT_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct spi_delay delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) nents = dw_readl(dws, DW_SPI_TXFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) delay.unit = SPI_DELAY_UNIT_SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) while (dw_spi_dma_tx_busy(dws) && retry--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spi_delay_exec(&delay, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (retry < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&dws->master->dev, "Tx hanged up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * channel will clear a corresponding bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void dw_spi_dma_tx_done(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct dw_spi *dws = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clear_bit(TX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (test_bit(RX_BUSY, &dws->dma_chan_busy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) complete(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int dw_spi_dma_config_tx(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct dma_slave_config txconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) memset(&txconf, 0, sizeof(txconf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) txconf.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) txconf.dst_addr = dws->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) txconf.dst_maxburst = dws->txburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) txconf.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return dmaengine_slave_config(dws->txchan, &txconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!txdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) txdesc->callback = dw_spi_dma_tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) txdesc->callback_param = dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cookie = dmaengine_submit(txdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dmaengine_terminate_sync(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set_bit(TX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int retry = SPI_WAIT_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct spi_delay delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long ns, us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * It's unlikely that DMA engine is still doing the data fetching, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * if it's let's give it some reasonable time. The timeout calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * is based on the synchronous APB/SSI reference clock rate, on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * number of data entries left in the Rx FIFO, times a number of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * periods normally needed for a single APB read/write transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * without PREADY signal utilized (which is true for the DW APB SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * controller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) nents = dw_readl(dws, DW_SPI_RXFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ns <= NSEC_PER_USEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) delay.unit = SPI_DELAY_UNIT_NSECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) delay.value = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) delay.value = clamp_val(us, 0, USHRT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) while (dw_spi_dma_rx_busy(dws) && retry--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) spi_delay_exec(&delay, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (retry < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(&dws->master->dev, "Rx hanged up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * channel will clear a corresponding bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void dw_spi_dma_rx_done(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dw_spi *dws = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clear_bit(RX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (test_bit(TX_BUSY, &dws->dma_chan_busy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) complete(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int dw_spi_dma_config_rx(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct dma_slave_config rxconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memset(&rxconf, 0, sizeof(rxconf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rxconf.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rxconf.src_addr = dws->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rxconf.src_maxburst = dws->rxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rxconf.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return dmaengine_slave_config(dws->rxchan, &rxconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct dma_async_tx_descriptor *rxdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!rxdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) rxdesc->callback = dw_spi_dma_rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rxdesc->callback_param = dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cookie = dmaengine_submit(rxdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dmaengine_terminate_sync(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) set_bit(RX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u16 imr, dma_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Setup DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = dw_spi_dma_config_tx(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (xfer->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = dw_spi_dma_config_rx(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Set the DMA handshaking interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_ctrl = SPI_DMA_TDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dma_ctrl |= SPI_DMA_RDMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Set the interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) imr = SPI_INT_TXOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) imr |= SPI_INT_RXUI | SPI_INT_RXOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spi_umask_intr(dws, imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reinit_completion(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dws->transfer_handler = dw_spi_dma_transfer_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int dw_spi_dma_transfer_all(struct dw_spi *dws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Submit the DMA Tx transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto err_clear_dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Submit the DMA Rx transfer if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (xfer->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) xfer->rx_sg.nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto err_clear_dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* rx must be started before tx due to spi instinct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dma_async_issue_pending(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dma_async_issue_pending(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err_clear_dmac:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dw_writel(dws, DW_SPI_DMACR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * In case if at least one of the requested DMA channels doesn't support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * hardware accelerated SG list entries traverse, the DMA driver will most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * likely work that around by performing the IRQ-based SG list entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * resubmission. That might and will cause a problem if the DMA Tx channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * recharged and re-executed before the Rx DMA channel. Due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * non-deterministic IRQ-handler execution latency the DMA Tx channel will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * start pushing data to the SPI bus before the Rx DMA channel is even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * the DMA Rx channel being recharged and re-executed will eventually be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * overflown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * In order to solve the problem we have to feed the DMA engine with SG list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * and rx_sg lists may have different number of entries of different lengths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * (though total length should match) let's virtually split the SG-lists to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * set of DMA transfers, which length is a minimum of the ordered SG-entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * lengths. An ASCII-sketch of the implemented algo is following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * xfer->len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * |___________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * tx_sg list: |___|____|__|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * rx_sg list: |_|____|____|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * DMA transfers: |_|_|__|_|__|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Note in order to have this workaround solving the denoted problem the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * engine driver should properly initialize the max_sg_burst capability and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * the DMA device max segment size parameter with maximum data block size the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * DMA engine supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int dw_spi_dma_transfer_one(struct dw_spi *dws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int tx_len = 0, rx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int base, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) sg_init_table(&tx_tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sg_init_table(&rx_tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (base = 0, len = 0; base < xfer->len; base += len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Fetch next Tx DMA data chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) tx_len = sg_dma_len(tx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Fetch next Rx DMA data chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rx_len = sg_dma_len(rx_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) len = min(tx_len, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sg_dma_len(&tx_tmp) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) sg_dma_len(&rx_tmp) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Submit DMA Tx transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Submit DMA Rx transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Rx must be started before Tx due to SPI instinct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dma_async_issue_pending(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dma_async_issue_pending(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Here we only need to wait for the DMA transfer to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * finished since SPI controller is kept enabled during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * procedure this loop implements and there is no risk to lose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * data left in the Tx/Rx FIFOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reinit_completion(&dws->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) sg_dma_address(&tx_tmp) += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) sg_dma_address(&rx_tmp) += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tx_len -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rx_len -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dw_writel(dws, DW_SPI_DMACR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Execute normal DMA-based transfer (which submits the Rx and Tx SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * lists directly to the DMA engine at once) if either full hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * accelerated SG list traverse is supported by both channels, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Tx-only SPI transfer is requested, or the DMA engine is capable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * handle both SG lists on hardware accelerated basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = dw_spi_dma_transfer_all(dws, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = dw_spi_dma_transfer_one(dws, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (dws->master->cur_msg->status == -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = dw_spi_dma_wait_tx_done(dws, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = dw_spi_dma_wait_rx_done(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static void dw_spi_dma_stop(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dmaengine_terminate_sync(dws->txchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) clear_bit(TX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dmaengine_terminate_sync(dws->rxchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) clear_bit(RX_BUSY, &dws->dma_chan_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .dma_init = dw_spi_dma_init_mfld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .dma_exit = dw_spi_dma_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .dma_setup = dw_spi_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .can_dma = dw_spi_can_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .dma_transfer = dw_spi_dma_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .dma_stop = dw_spi_dma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void dw_spi_dma_setup_mfld(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dws->dma_ops = &dw_spi_dma_mfld_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) EXPORT_SYMBOL_GPL(dw_spi_dma_setup_mfld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .dma_init = dw_spi_dma_init_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .dma_exit = dw_spi_dma_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .dma_setup = dw_spi_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .can_dma = dw_spi_can_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .dma_transfer = dw_spi_dma_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .dma_stop = dw_spi_dma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void dw_spi_dma_setup_generic(struct dw_spi *dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dws->dma_ops = &dw_spi_dma_generic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EXPORT_SYMBOL_GPL(dw_spi_dma_setup_generic);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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