^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Serge Semin <Sergey.Semin@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Baikal-T1 DW APB SPI and System Boot SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mux/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "spi-dw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BT1_BOOT_DIRMAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BT1_BOOT_REGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dw_spi_bt1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct dw_spi dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mux_control *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef CONFIG_SPI_DW_BT1_DIRMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) resource_size_t map_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define to_dw_spi_bt1(_ctlr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) container_of(spi_controller_get_devdata(_ctlr), struct dw_spi_bt1, dws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) typedef int (*dw_spi_bt1_init_cb)(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct dw_spi_bt1 *dwsbt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifdef CONFIG_SPI_DW_BT1_DIRMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int dw_spi_bt1_dirmap_create(struct spi_mem_dirmap_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!dwsbt1->map ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Make sure the requested region doesn't go out of the physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * mapped flash memory bounds and the operation is read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (desc->info.offset + desc->info.length > dwsbt1->map_len ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Directly mapped SPI memory region is only accessible in the dword chunks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * That's why we have to create a dedicated read-method to copy data from there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * to the passed buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void dw_spi_bt1_dirmap_copy_from_map(void *to, void __iomem *from, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) size_t shift, chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * We split the copying up into the next three stages: unaligned head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * aligned body, unaligned tail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) shift = (size_t)from & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) chunk = min_t(size_t, 4 - shift, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data = readl_relaxed(from - shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) memcpy(to, (char *)&data + shift, chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) from += chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) to += chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) len -= chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) while (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) data = readl_relaxed(from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) memcpy(to, &data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) from += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) to += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) data = readl_relaxed(from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memcpy(to, &data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static ssize_t dw_spi_bt1_dirmap_read(struct spi_mem_dirmap_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u64 offs, size_t len, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dw_spi *dws = &dwsbt1->dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct spi_mem *mem = desc->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct dw_spi_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Make sure the requested operation length is valid. Truncate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * length if it's greater than the length of the MMIO region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (offs >= dwsbt1->map_len || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) len = min_t(size_t, len, dwsbt1->map_len - offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Collect the controller configuration required by the operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cfg.tmode = SPI_TMOD_EPROMREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cfg.dfs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cfg.ndf = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cfg.freq = mem->spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Make sure the corresponding CS is de-asserted on transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dw_spi_set_cs(mem->spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spi_enable_chip(dws, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dw_spi_update_config(dws, mem->spi, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spi_umask_intr(dws, SPI_INT_RXFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spi_enable_chip(dws, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Enable the transparent mode of the System Boot Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * The SPI core IO should have been locked before calling this method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * so noone would be touching the controller' registers during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * dirmap operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = mux_control_select(dwsbt1->mux, BT1_BOOT_DIRMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dw_spi_bt1_dirmap_copy_from_map(buf, dwsbt1->map + offs, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mux_control_deselect(dwsbt1->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dw_spi_set_cs(mem->spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = dw_spi_check_status(dws, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret ?: len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int dw_spi_bt1_std_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct dw_spi_bt1 *dwsbt1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct dw_spi *dws = &dwsbt1->dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dws->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (dws->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return dws->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dws->num_cs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Baikal-T1 Normal SPI Controllers don't always keep up with full SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * bus speed especially when it comes to the concurrent access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * APB bus resources. Thus we have no choice but to set a constraint on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * the SPI bus frequency for the memory operations which require to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * read/write data as fast as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dws->max_mem_freq = 20000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dw_spi_dma_setup_generic(dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int dw_spi_bt1_sys_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dw_spi_bt1 *dwsbt1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct resource *mem __maybe_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct dw_spi *dws = &dwsbt1->dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Baikal-T1 System Boot Controller is equipped with a mux, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * switches between the directly mapped SPI flash access mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * IO access to the DW APB SSI registers. Note the mux controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * must be setup to preserve the registers being accessible by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * (on idle-state).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dwsbt1->mux = devm_mux_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (IS_ERR(dwsbt1->mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return PTR_ERR(dwsbt1->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Directly mapped SPI flash memory is a 16MB MMIO region, which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * used to access a peripheral memory device just by reading/writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * data from/to it. Note the system APB bus will stall during each IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * from/to the dirmap region until the operation is finished. So don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * use it concurrently with time-critical tasks (like the SPI memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * operations implemented in the DW APB SSI driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef CONFIG_SPI_DW_BT1_DIRMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dwsbt1->map = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!IS_ERR(dwsbt1->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dwsbt1->map_len = (mem->end - mem->start + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dws->mem_ops.dirmap_create = dw_spi_bt1_dirmap_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dws->mem_ops.dirmap_read = dw_spi_bt1_dirmap_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dwsbt1->map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * There is no IRQ, no DMA and just one CS available on the System Boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dws->irq = IRQ_NOTCONNECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dws->num_cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Baikal-T1 System Boot SPI Controller doesn't keep up with the full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * SPI bus speed due to relatively slow APB bus and races for it'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * resources from different CPUs. The situation is worsen by a small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * FIFOs depth (just 8 words). It works better in a single CPU mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * though, but still tends to be not fast enough at low CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (num_possible_cpus() > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dws->max_mem_freq = 10000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dws->max_mem_freq = 20000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int dw_spi_bt1_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dw_spi_bt1_init_cb init_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct dw_spi_bt1 *dwsbt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct dw_spi *dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dwsbt1 = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_bt1), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!dwsbt1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dws = &dwsbt1->dws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ERR(dws->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return PTR_ERR(dws->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dws->paddr = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dwsbt1->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (IS_ERR(dwsbt1->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return PTR_ERR(dwsbt1->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = clk_prepare_enable(dwsbt1->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dws->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dws->reg_io_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dws->max_freq = clk_get_rate(dwsbt1->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!dws->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) init_func = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = init_func(pdev, dwsbt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = dw_spi_add_host(&pdev->dev, dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) platform_set_drvdata(pdev, dwsbt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_disable_unprepare(dwsbt1->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int dw_spi_bt1_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dw_spi_bt1 *dwsbt1 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dw_spi_remove_host(&dwsbt1->dws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk_disable_unprepare(dwsbt1->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct of_device_id dw_spi_bt1_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .compatible = "baikal,bt1-ssi", .data = dw_spi_bt1_std_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .compatible = "baikal,bt1-sys-ssi", .data = dw_spi_bt1_sys_init},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_DEVICE_TABLE(of, dw_spi_bt1_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct platform_driver dw_spi_bt1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .probe = dw_spi_bt1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .remove = dw_spi_bt1_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "bt1-sys-ssi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .of_match_table = dw_spi_bt1_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) module_platform_driver(dw_spi_bt1_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DESCRIPTION("Baikal-T1 System Boot SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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