^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Diolan DLN-2 USB-SPI adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/dln2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DLN2_SPI_MODULE_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* SPI commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DLN2_SPI_READ DLN2_SPI_CMD(0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DLN2_SPI_MAX_XFER_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DLN2_TRANSFERS_WAIT_COMPLETE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DLN2_TRANSFERS_CANCEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dln2_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * This buffer will be used mainly for read/write operations. Since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * they're quite large, we cannot use the stack. Protection is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * needed because all SPI communication is serialized by the SPI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Enable/Disable SPI module. The disable command will wait for transfers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * complete first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 wait_for_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned len = sizeof(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cmd = DLN2_SPI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) len -= sizeof(tx.wait_for_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cmd = DLN2_SPI_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Select/unselect multiple CS lines. The selected lines will be automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * toggled LOW/HIGH by the board firmware during transfers, provided they're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * enabled first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * will toggle the lines LOW/HIGH automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * According to Diolan docs, "a slave device can be selected by changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * the corresponding bit value to 0". The rest must be set to 1. Hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the bitwise NOT in front.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tx.cs = ~cs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Select one CS line. The other lines will be un-selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return dln2_spi_cs_set(dln2, BIT(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Enable/disable CS lines for usage. The module has to be disabled first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tx.cs = cs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return dln2_spi_cs_enable(dln2, cs_mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le16 cs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned rx_len = sizeof(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (rx_len < sizeof(rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *cs_num = le16_to_cpu(rx.cs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned rx_len = sizeof(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (rx_len < sizeof(rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *freq = le32_to_cpu(rx.speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Get bus min/max frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *fmin, *fmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Set the bus speed. The module will automatically round down to the closest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * available frequency and returns it. The module has to be disabled first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __le32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } __packed tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __le32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int rx_len = sizeof(rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tx.speed = cpu_to_le32(speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (rx_len < sizeof(rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Change CPOL & CPHA. The module has to be disabled first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tx.mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Change frame size. The module has to be disabled first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tx.bpw = bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &tx, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 *bpw_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 frame_sizes[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } *rx = dln2->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned rx_len = sizeof(*rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &tx, sizeof(tx), rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (rx_len < sizeof(*rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (rx->count > ARRAY_SIZE(rx->frame_sizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *bpw_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) for (i = 0; i < rx->count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Copy the data to DLN2 buffer and change the byte order to LE, requested by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * DLN2 module. SPI core makes sure that the data length is a multiple of word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) memcpy(dln2_buf, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (bpw <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memcpy(dln2_buf, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else if (bpw <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __le16 *d = (__le16 *)dln2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u16 *s = (u16 *)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) len = len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *d++ = cpu_to_le16p(s++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __le32 *d = (__le32 *)dln2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 *s = (u32 *)src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) len = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *d++ = cpu_to_le32p(s++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * buffer is LE ordered. SPI core makes sure that the data length is a multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * sure we avoid unaligned accesses for 32 bit case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) memcpy(dest, dln2_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (bpw <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) memcpy(dest, dln2_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else if (bpw <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 *d = (u16 *)dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __le16 *s = (__le16 *)dln2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) len = len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *d++ = le16_to_cpup(s++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 *d = (u32 *)dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __le32 *s = (__le32 *)dln2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) len = len / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *d++ = get_unaligned_le32(s++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Perform one write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 data_len, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 buf[DLN2_SPI_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } __packed *tx = dln2->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (data_len > DLN2_SPI_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tx->port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tx->size = cpu_to_le16(data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tx->attr = attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Perform one read operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u16 data_len, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } __packed tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 buf[DLN2_SPI_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } __packed *rx = dln2->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned rx_len = sizeof(*rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (data_len > DLN2_SPI_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tx.port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tx.size = cpu_to_le16(data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tx.attr = attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (rx_len < sizeof(rx->size) + data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (le16_to_cpu(rx->size) != data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Perform one write & read operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 *rx_data, u16 data_len, u8 attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 buf[DLN2_SPI_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } __packed *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 buf[DLN2_SPI_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } __packed *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned tx_len, rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sizeof(*rx) > DLN2_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (data_len > DLN2_SPI_MAX_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Since this is a pseudo full-duplex communication, we're perfectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * safe to use the same buffer for both tx and rx. When DLN2 sends the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * response back, with the rx data, we don't need the tx buffer anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tx = dln2->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rx = dln2->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) tx->port = dln2->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tx->size = cpu_to_le16(data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tx->attr = attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rx_len = sizeof(*rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rx, &rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (rx_len < sizeof(rx->size) + data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (le16_to_cpu(rx->size) != data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Read/Write wrapper. It will automatically split an operation into multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * single ones due to device buffer constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u8 *rx_data, u16 data_len, u8 attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 temp_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u16 remaining = data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) len = DLN2_SPI_MAX_XFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) len = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) temp_attr = attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) offset = data_len - remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (tx_data && rx_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = dln2_spi_read_write_one(dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tx_data + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) rx_data + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) len, temp_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else if (tx_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = dln2_spi_write_one(dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tx_data + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) len, temp_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else if (rx_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = dln2_spi_read_one(dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rx_data + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) len, temp_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) remaining -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } while (remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int dln2_spi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct spi_device *spi = message->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (dln2->cs != spi->chip_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dln2->cs = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u8 bpw, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) bool bus_setup_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dln2->bpw != bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!bus_setup_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = dln2_spi_enable(dln2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (dln2->speed != speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = dln2_spi_set_speed(dln2, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dln2->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (dln2->mode != mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = dln2_spi_set_mode(dln2, mode & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dln2->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (dln2->bpw != bpw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = dln2_spi_set_bpw(dln2, bpw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dln2->bpw = bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return dln2_spi_enable(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int dln2_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u8 attr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) xfer->bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) xfer->len, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(&dln2->pdev->dev, "write/read failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int dln2_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct dln2_spi *dln2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!dln2->buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dln2->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dln2->master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dln2->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dln2->port = pdata->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* cs/mode can never be 0xff, so the first transfer will set them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dln2->cs = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dln2->mode = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* disable SPI module before continuing with the setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = dln2_spi_enable(dln2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_err(&pdev->dev, "Failed to disable SPI module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_err(&pdev->dev, "Failed to get number of CS pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = dln2_spi_get_speed_range(dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &master->min_speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) &master->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = dln2_spi_get_supported_frame_sizes(dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) &master->bits_per_word_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = dln2_spi_cs_enable_all(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(&pdev->dev, "Failed to enable CS pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) master->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) master->mode_bits = SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) master->prepare_message = dln2_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) master->transfer_one = dln2_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* enable SPI module, we're good to go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = dln2_spi_enable(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(&pdev->dev, "Failed to enable SPI module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto exit_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DLN2_RPM_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ret = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&pdev->dev, "Failed to register master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto exit_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) exit_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (dln2_spi_enable(dln2, false) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(&pdev->dev, "Failed to disable SPI module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) exit_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int dln2_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (dln2_spi_enable(dln2, false) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_err(&pdev->dev, "Failed to disable SPI module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int dln2_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!pm_runtime_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = dln2_spi_enable(dln2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * USB power may be cut off during sleep. Resetting the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * parameters will force the board to be set up before first transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dln2->cs = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dln2->speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dln2->bpw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dln2->mode = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int dln2_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!pm_runtime_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = dln2_spi_cs_enable_all(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = dln2_spi_enable(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int dln2_spi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return dln2_spi_enable(dln2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int dln2_spi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct dln2_spi *dln2 = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return dln2_spi_enable(dln2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct dev_pm_ops dln2_spi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dln2_spi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct platform_driver spi_dln2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "dln2-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pm = &dln2_spi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .probe = dln2_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .remove = dln2_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) module_platform_driver(spi_dln2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MODULE_ALIAS("platform:dln2-spi");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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