^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 EF Johnson Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_data/spi-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CS_DEFAULT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPIFMT_PHASE_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPIFMT_POLARITY_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPIFMT_DISTIMER_MASK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPIFMT_SHIFTDIR_MASK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPIFMT_WAITENA_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPIFMT_PARITYENA_MASK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPIFMT_ODD_PARITY_MASK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPIFMT_WDELAY_MASK 0x3f000000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPIFMT_WDELAY_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPIFMT_PRESCALE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* SPIPC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPIINT_MASKALL 0x0101035F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPIINT_MASKINT 0x0000015F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_INTLVL_1 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_INTLVL_0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* SPIDAT1 (upper 16 bit defines) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPIDAT1_CSHOLD_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPIDAT1_WDEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SPIGCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPIGCR1_CLKMOD_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPIGCR1_MASTER_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPIGCR1_POWERDOWN_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPIGCR1_LOOPBACK_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPIGCR1_SPIENA_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* SPIBUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPIBUF_TXFULL_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPIBUF_RXEMPTY_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* SPIDELAY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPIDELAY_C2TDELAY_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPIDELAY_T2CDELAY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPIDELAY_T2EDELAY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPIDELAY_C2EDELAY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPIDELAY_C2EDELAY_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Error Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPIFLG_DLEN_ERR_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPIFLG_TIMEOUT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPIFLG_PARERR_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPIFLG_DESYNC_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPIFLG_BITERR_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPIFLG_OVRRUN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) | SPIFLG_OVRRUN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPIINT_DMA_REQ_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* SPI Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPIGCR0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPIGCR1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPIINT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPILVL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPIFLG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPIPC0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPIDAT1 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPIBUF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPIDELAY 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPIDEF 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPIFMT0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DMA_MIN_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SPI Controller driver's private data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct davinci_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct spi_bitbang bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) resource_size_t pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const void *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int rcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int wcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct davinci_spi_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*get_rx)(u32 rx_data, struct davinci_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 (*get_tx)(struct davinci_spi *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 *bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 prescaler_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct davinci_spi_config davinci_spi_default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (dspi->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 *rx = dspi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *rx++ = (u8)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dspi->rx = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (dspi->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 *rx = dspi->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *rx++ = (u16)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dspi->rx = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (dspi->tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const u8 *tx = dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) data = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dspi->tx = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (dspi->tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const u16 *tx = dspi->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) data = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dspi->tx = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline void set_io_bits(void __iomem *addr, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 v = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) iowrite32(v, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void clear_io_bits(void __iomem *addr, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 v = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) iowrite32(v, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Interface to control the chip select signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void davinci_spi_chipselect(struct spi_device *spi, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct davinci_spi_config *spicfg = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 chip_sel = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 spidat1 = CS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* program delay transfers if tx_delay is non zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (spicfg && spicfg->wdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spidat1 |= SPIDAT1_WDEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Board specific chip select logic decides the polarity and cs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * line for the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (spi->cs_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (value == BITBANG_CS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) gpiod_set_value(spi->cs_gpiod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gpiod_set_value(spi->cs_gpiod, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (value == BITBANG_CS_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!(spi->mode & SPI_CS_WORD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spidat1 |= SPIDAT1_CSHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spidat1 &= ~(0x1 << chip_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * davinci_spi_get_prescale - Calculates the correct prescale value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @dspi: the controller data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @max_speed_hz: the maximum rate the SPI clock can run at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * This function calculates the prescale value that generates a clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * less than or equal to the specified maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Returns: calculated prescale value for easy programming into SPI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * or negative error number if valid prescalar cannot be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Subtract 1 to match what will be programmed into SPI register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret < dspi->prescaler_limit || ret > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * davinci_spi_setup_transfer - This functions will determine transfer method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @spi: spi device on which data transfer to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @t: spi transfer in which transfer info is filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * This function determines data transfer method (8/16/32 bit transfer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * It will also set the SPI Clock Control register according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * SPI slave device freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int davinci_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct davinci_spi_config *spicfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 hz = 0, spifmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spicfg = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!spicfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spicfg = &davinci_spi_default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* if bits_per_word is not set then set it default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Assign function pointer to appropriate transfer method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * 8bit, 16bit or 32bit transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dspi->get_rx = davinci_spi_rx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dspi->get_tx = davinci_spi_tx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dspi->bytes_per_word[spi->chip_select] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dspi->get_rx = davinci_spi_rx_buf_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dspi->get_tx = davinci_spi_tx_buf_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dspi->bytes_per_word[spi->chip_select] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Set up SPIFMTn register, unique to this chipselect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) prescale = davinci_spi_get_prescale(dspi, hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (prescale < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (spi->mode & SPI_LSB_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spifmt |= SPIFMT_SHIFTDIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spifmt |= SPIFMT_POLARITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!(spi->mode & SPI_CPHA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spifmt |= SPIFMT_PHASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Assume wdelay is used only on SPI peripherals that has this field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * in SPIFMTn register and when it's configured from board file or DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (spicfg->wdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) & SPIFMT_WDELAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Version 1 hardware supports two basic SPI modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * - Standard SPI mode uses 4 pins, with chipselect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * (distinct from SPI_3WIRE, with just one data wire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * or similar variants without MOSI or without MISO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Version 2 hardware supports an optional handshaking signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * so it can support two more modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * - 5 pin SPI variant is standard SPI plus SPI_READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (dspi->version == SPI_VERSION_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (spicfg->odd_parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spifmt |= SPIFMT_ODD_PARITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (spicfg->parity_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spifmt |= SPIFMT_PARITYENA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (spicfg->timer_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spifmt |= SPIFMT_DISTIMER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) & SPIDELAY_C2TDELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) & SPIDELAY_T2CDELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (spi->mode & SPI_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spifmt |= SPIFMT_WAITENA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) & SPIDELAY_T2EDELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) & SPIDELAY_C2EDELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) iowrite32(delay, dspi->base + SPIDELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) iowrite32(spifmt, dspi->base + SPIFMT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int davinci_spi_of_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct davinci_spi_config *spicfg = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (spicfg == NULL && np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!spicfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *spicfg = davinci_spi_default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* override with dt configured values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spicfg->wdelay = (u8)prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spi->controller_data = spicfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (dspi->dma_rx && dspi->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spicfg->io_type = SPI_IO_TYPE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * davinci_spi_setup - This functions will set default transfer method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @spi: spi device on which data transfer to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * This functions sets the default transfer method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int davinci_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool internal_cs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!(spi->mode & SPI_NO_CS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (np && spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) internal_cs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (internal_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (spi->mode & SPI_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (spi->mode & SPI_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return davinci_spi_of_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void davinci_spi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct davinci_spi_config *spicfg = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spi->controller_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (spi->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) kfree(spicfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static bool davinci_spi_can_dma(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct davinci_spi_config *spicfg = spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bool can_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (spicfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (xfer->len >= DMA_MIN_BYTES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) !is_vmalloc_addr(xfer->rx_buf) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) !is_vmalloc_addr(xfer->tx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct device *sdev = dspi->bitbang.master->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (int_status & SPIFLG_TIMEOUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(sdev, "SPI Time-out Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (int_status & SPIFLG_DESYNC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(sdev, "SPI Desynchronization Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (int_status & SPIFLG_BITERR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(sdev, "SPI Bit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (dspi->version == SPI_VERSION_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (int_status & SPIFLG_DLEN_ERR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(sdev, "SPI Data Length Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (int_status & SPIFLG_PARERR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(sdev, "SPI Parity Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (int_status & SPIFLG_OVRRUN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(sdev, "SPI Data Overrun error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(sdev, "SPI Buffer Init Active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * davinci_spi_process_events - check for and handle any SPI controller events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @dspi: the controller data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * This function will check the SPIFLG register and handle any events that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * detected there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int davinci_spi_process_events(struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 buf, status, errors = 0, spidat1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) buf = ioread32(dspi->base + SPIBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dspi->get_rx(buf & 0xFFFF, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dspi->rcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) status = ioread32(dspi->base + SPIFLG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (unlikely(status & SPIFLG_ERROR_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) errors = status & SPIFLG_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spidat1 = ioread32(dspi->base + SPIDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dspi->wcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spidat1 &= ~0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) spidat1 |= 0xFFFF & dspi->get_tx(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) iowrite32(spidat1, dspi->base + SPIDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void davinci_spi_dma_rx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct davinci_spi *dspi = (struct davinci_spi *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dspi->rcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!dspi->wcount && !dspi->rcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) complete(&dspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void davinci_spi_dma_tx_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct davinci_spi *dspi = (struct davinci_spi *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dspi->wcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!dspi->wcount && !dspi->rcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) complete(&dspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * davinci_spi_bufs - functions which will handle transfer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @spi: spi device on which data transfer to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @t: spi transfer in which transfer info is filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * This function will put data to be transferred into data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * of SPI controller and then wait until the completion will be marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * by the IRQ Handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int data_type, ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 tx_data, spidat1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct davinci_spi_config *spicfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct davinci_spi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pdata = &dspi->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) spicfg = (struct davinci_spi_config *)spi->controller_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!spicfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) spicfg = &davinci_spi_default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* convert len to words based on bits_per_word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) data_type = dspi->bytes_per_word[spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dspi->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dspi->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dspi->wcount = t->len / data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dspi->rcount = dspi->wcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) spidat1 = ioread32(dspi->base + SPIDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reinit_completion(&dspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!davinci_spi_can_dma(spi->master, spi, t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (spicfg->io_type != SPI_IO_TYPE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dspi->wcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) tx_data = dspi->get_tx(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spidat1 &= 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spidat1 |= tx_data & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) iowrite32(spidat1, dspi->base + SPIDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct dma_slave_config dma_rx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .direction = DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .src_addr = (unsigned long)dspi->pbase + SPIBUF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .src_addr_width = data_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .src_maxburst = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct dma_slave_config dma_tx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .direction = DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .dst_addr_width = data_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .dst_maxburst = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct dma_async_tx_descriptor *rxdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!rxdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto err_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* To avoid errors when doing rx-only transfers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * many SG entries (> 20), use the rx buffer as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * dummy tx buffer so that dma reloads are done at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * same time for rx and tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) t->tx_sg.sgl = t->rx_sg.sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) t->tx_sg.nents = t->rx_sg.nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!txdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto err_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rxdesc->callback = davinci_spi_dma_rx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) rxdesc->callback_param = (void *)dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) txdesc->callback = davinci_spi_dma_tx_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) txdesc->callback_param = (void *)dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (pdata->cshold_bug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dmaengine_submit(rxdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dmaengine_submit(txdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dma_async_issue_pending(dspi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dma_async_issue_pending(dspi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Wait for the transfer to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (spicfg->io_type != SPI_IO_TYPE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) errors = SPIFLG_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) while (dspi->rcount > 0 || dspi->wcount > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) errors = davinci_spi_process_events(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (davinci_spi_can_dma(spi->master, spi, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Check for bit error, desync error,parity error,timeout error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * receive overflow errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (errors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = davinci_spi_check_error(dspi, errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) WARN(!ret, "%s: error reported but no error found!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_name(&spi->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (dspi->rcount != 0 || dspi->wcount != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(&spi->dev, "SPI data transfer error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) err_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * dummy_thread_fn - dummy thread function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @irq: IRQ number for this SPI Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @data: structure for SPI Master controller davinci_spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * This is to satisfy the request_threaded_irq() API so that the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * handler is called in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static irqreturn_t dummy_thread_fn(s32 irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * davinci_spi_irq - Interrupt handler for SPI Master Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * @irq: IRQ number for this SPI Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * @data: structure for SPI Master controller davinci_spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * ISR will determine that interrupt arrives either for READ or WRITE command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * According to command it will do the appropriate action. It will check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * transfer length and if it is not zero then dispatch transfer command again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * If transfer length is zero then it will indicate the COMPLETION so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * davinci_spi_bufs function can go ahead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static irqreturn_t davinci_spi_irq(s32 irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct davinci_spi *dspi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) status = davinci_spi_process_events(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (unlikely(status != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if ((!dspi->rcount && !dspi->wcount) || status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) complete(&dspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int davinci_spi_request_dma(struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct device *sdev = dspi->bitbang.master->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dspi->dma_rx = dma_request_chan(sdev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (IS_ERR(dspi->dma_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return PTR_ERR(dspi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dspi->dma_tx = dma_request_chan(sdev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (IS_ERR(dspi->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dma_release_channel(dspi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return PTR_ERR(dspi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* OF SPI data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct davinci_spi_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 prescaler_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const struct davinci_spi_of_data dm6441_spi_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .version = SPI_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .prescaler_limit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct davinci_spi_of_data da830_spi_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .version = SPI_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .prescaler_limit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const struct davinci_spi_of_data keystone_spi_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .version = SPI_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .prescaler_limit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct of_device_id davinci_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .compatible = "ti,dm6441-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .data = &dm6441_spi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .compatible = "ti,da830-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .data = &da830_spi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .compatible = "ti,keystone-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .data = &keystone_spi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * spi_davinci_get_pdata - Get platform data from DTS binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * @pdev: ptr to platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * @dspi: ptr to driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Parses and populates pdata in dspi from device tree bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * NOTE: Not all platform data params are supported currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int spi_davinci_get_pdata(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct davinci_spi_of_data *spi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct davinci_spi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int num_cs, intr_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pdata = &dspi->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) match = of_match_device(davinci_spi_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) spi_data = (struct davinci_spi_of_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pdata->version = spi_data->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pdata->prescaler_limit = spi_data->prescaler_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * default num_cs is 1 and all chipsel are internal to the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * indicated by chip_sel being NULL or cs_gpios being NULL or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * set to -ENOENT. num-cs includes internal as well as gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * indicated by chip_sel being NULL. GPIO based CS is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * supported yet in DT bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) num_cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) of_property_read_u32(node, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pdata->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pdata->intr_line = intr_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int spi_davinci_get_pdata(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct davinci_spi *dspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * davinci_spi_probe - probe function for SPI Master Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * @pdev: platform_device structure which contains plateform specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * According to Linux Device Model this function will be invoked by Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * with platform_device struct which contains the device specific info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * This function will map the SPI controller's memory, register IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * Reset SPI controller and setting its registers to default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * It will invoke spi_bitbang_start to create work queue so that client driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * can register transfer method to work queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int davinci_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct davinci_spi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 spipc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (dev_get_platdata(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dspi->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* update dspi pdata with that from the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = spi_davinci_get_pdata(pdev, dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* pdata in dspi is now updated and point pdata to that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pdata = &dspi->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pdata->num_chipselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) sizeof(*dspi->bytes_per_word),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (dspi->bytes_per_word == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dspi->pbase = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dspi->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (IS_ERR(dspi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = PTR_ERR(dspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) init_completion(&dspi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dspi->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dspi->bitbang.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dspi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (IS_ERR(dspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret = clk_prepare_enable(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) master->num_chipselect = pdata->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_GPIO_SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) master->setup = davinci_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) master->cleanup = davinci_spi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) master->can_dma = davinci_spi_can_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dspi->bitbang.chipselect = davinci_spi_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dspi->prescaler_limit = pdata->prescaler_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dspi->version = pdata->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (dspi->version == SPI_VERSION_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dspi->bitbang.flags |= SPI_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dspi->bitbang.txrx_bufs = davinci_spi_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = davinci_spi_request_dma(dspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dspi->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dspi->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dspi->get_rx = davinci_spi_rx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dspi->get_tx = davinci_spi_tx_buf_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Reset In/OUT SPI module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) iowrite32(0, dspi->base + SPIGCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) iowrite32(1, dspi->base + SPIGCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) iowrite32(spipc0, dspi->base + SPIPC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (pdata->intr_line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* master mode default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = spi_bitbang_start(&dspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) goto free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (dspi->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dma_release_channel(dspi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dma_release_channel(dspi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) clk_disable_unprepare(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * davinci_spi_remove - remove function for SPI Master Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * @pdev: platform_device structure which contains plateform specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * This function will do the reverse action of davinci_spi_probe function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * It will free the IRQ and SPI controller's memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * It will also call spi_bitbang_stop to destroy the work queue which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * created by spi_bitbang_start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int davinci_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct davinci_spi *dspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) spi_bitbang_stop(&dspi->bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) clk_disable_unprepare(dspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (dspi->dma_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dma_release_channel(dspi->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dma_release_channel(dspi->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static struct platform_driver davinci_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .name = "spi_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .of_match_table = of_match_ptr(davinci_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .probe = davinci_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .remove = davinci_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) module_platform_driver(davinci_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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