^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale/Motorola Coldfire Queued SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfqspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRIVER_NAME "mcfqspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCFQSPI_QMR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCFQSPI_QMR_MSTR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCFQSPI_QMR_CPOL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCFQSPI_QMR_CPHA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFQSPI_QDLYR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFQSPI_QDLYR_SPE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCFQSPI_QWR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCFQSPI_QWR_HALT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCFQSPI_QWR_WREN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCFQSPI_QWR_CSIV 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCFQSPI_QIR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCFQSPI_QIR_WCEFB 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCFQSPI_QIR_ABRTB 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCFQSPI_QIR_ABRTL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCFQSPI_QIR_WCEFE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCFQSPI_QIR_ABRTE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCFQSPI_QIR_SPIFE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCFQSPI_QIR_WCEF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCFQSPI_QIR_ABRT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCFQSPI_QIR_SPIF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCFQSPI_QAR 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCFQSPI_QAR_TXBUF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCFQSPI_QAR_RXBUF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCFQSPI_QAR_CMDBUF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCFQSPI_QDR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCFQSPI_QCR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCFQSPI_QCR_CONT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCFQSPI_QCR_BITSE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCFQSPI_QCR_DT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mcfqspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mcfqspi_cs_control *cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writew(val, mcfqspi->iobase + MCFQSPI_QMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writew(val, mcfqspi->iobase + MCFQSPI_QWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writew(val, mcfqspi->iobase + MCFQSPI_QIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writew(val, mcfqspi->iobase + MCFQSPI_QAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writew(val, mcfqspi->iobase + MCFQSPI_QDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return readw(mcfqspi->iobase + MCFQSPI_QDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool cs_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool cs_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return (mcfqspi->cs_control->setup) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (mcfqspi->cs_control->teardown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mcfqspi->cs_control->teardown(mcfqspi->cs_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static u8 mcfqspi_qmr_baud(u32 speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mcfqspi *mcfqspi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) wake_up(&mcfqspi->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const u8 *txbuf, u8 *rxbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned i, n, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) n = min(count, 16u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (txbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcfqspi_wr_qdr(mcfqspi, *txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mcfqspi_wr_qdr(mcfqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) count -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 qwr = 0xf08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mcfqspi_wr_qwr(mcfqspi, 0x700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mcfqspi_wr_qwr(mcfqspi, qwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mcfqspi_wr_qar(mcfqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) n = min(count, 8u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mcfqspi_wr_qar(mcfqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MCFQSPI_QAR_TXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mcfqspi_wr_qdr(mcfqspi, *txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) offset ^= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) count -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } while (count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mcfqspi_wr_qwr(mcfqspi, qwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) offset ^= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const u16 *txbuf, u16 *rxbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned i, n, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) n = min(count, 16u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (txbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mcfqspi_wr_qdr(mcfqspi, *txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mcfqspi_wr_qdr(mcfqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) count -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u16 qwr = 0xf08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mcfqspi_wr_qwr(mcfqspi, 0x700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mcfqspi_wr_qwr(mcfqspi, qwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mcfqspi_wr_qar(mcfqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) n = min(count, 8u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (txbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mcfqspi_wr_qar(mcfqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MCFQSPI_QAR_TXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mcfqspi_wr_qdr(mcfqspi, *txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) offset ^= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) count -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } while (count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mcfqspi_wr_qwr(mcfqspi, qwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) offset ^= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < n; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bool cs_high = spi->mode & SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int mcfqspi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u16 qmr = MCFQSPI_QMR_MSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) qmr |= t->bits_per_word << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) qmr |= MCFQSPI_QMR_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) qmr |= MCFQSPI_QMR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) qmr |= mcfqspi_qmr_baud(t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mcfqspi_wr_qmr(mcfqspi, qmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (t->bits_per_word == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) t->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mcfqspi_wr_qir(mcfqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int mcfqspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spi->chip_select, spi->mode & SPI_CS_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "bits per word %d, chip select %d, speed %d KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spi->bits_per_word, spi->chip_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int mcfqspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct mcfqspi *mcfqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct mcfqspi_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_dbg(&pdev->dev, "platform data is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!pdata->cs_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (master == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (IS_ERR(mcfqspi->iobase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) status = PTR_ERR(mcfqspi->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mcfqspi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (mcfqspi->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_dbg(&pdev->dev, "platform_get_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0, pdev->name, mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_dbg(&pdev->dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (IS_ERR(mcfqspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(&pdev->dev, "clk_get failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) status = PTR_ERR(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clk_prepare_enable(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) master->bus_num = pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) master->num_chipselect = pdata->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mcfqspi->cs_control = pdata->cs_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) status = mcfqspi_cs_setup(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(&pdev->dev, "error initializing cs_control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) init_waitqueue_head(&mcfqspi->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) master->setup = mcfqspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) master->set_cs = mcfqspi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) master->transfer_one = mcfqspi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) status = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_dbg(&pdev->dev, "spi_register_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mcfqspi_cs_teardown(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_disable_unprepare(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int mcfqspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* disable the hardware (set the baud rate to 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mcfqspi_cs_teardown(mcfqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_disable_unprepare(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int mcfqspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_disable(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int mcfqspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_enable(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int mcfqspi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk_disable(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int mcfqspi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk_enable(mcfqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct dev_pm_ops mcfqspi_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct platform_driver mcfqspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .driver.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .driver.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .driver.pm = &mcfqspi_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .probe = mcfqspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .remove = mcfqspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) module_platform_driver(mcfqspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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