^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011, 2012 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "spi-cavium.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static void octeon_spi_wait_ready(struct octeon_spi *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) union cvmx_mpi_sts mpi_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (loops++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __delay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) } while (mpi_sts.s.busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int octeon_spi_do_transfer(struct octeon_spi *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct spi_message *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct spi_transfer *xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool last_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) union cvmx_mpi_cfg mpi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) union cvmx_mpi_tx mpi_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool cpha, cpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) cpha = mode & SPI_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cpol = mode & SPI_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clkdiv = p->sys_freq / (2 * xfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mpi_cfg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mpi_cfg.s.clkdiv = clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mpi_cfg.s.idlelo = cpha != cpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mpi_cfg.s.cslate = cpha ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mpi_cfg.s.enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (spi->chip_select < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) p->cs_enax |= 1ull << (12 + spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mpi_cfg.u64 |= p->cs_enax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (mpi_cfg.u64 != p->last_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) p->last_cfg = mpi_cfg.u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tx_buf = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) rx_buf = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) len = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) while (len > OCTEON_SPI_MAX_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) d = *tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mpi_tx.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mpi_tx.s.csid = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mpi_tx.s.leavecs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) octeon_spi_wait_ready(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *rx_buf++ = (u8)v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) len -= OCTEON_SPI_MAX_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) d = *tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mpi_tx.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mpi_tx.s.csid = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (last_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mpi_tx.s.leavecs = xfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mpi_tx.s.leavecs = !xfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mpi_tx.s.txnum = tx_buf ? len : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mpi_tx.s.totnum = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) octeon_spi_wait_ready(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *rx_buf++ = (u8)v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spi_transfer_delay_exec(xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int octeon_spi_transfer_one_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct octeon_spi *p = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int total_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct spi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) list_for_each_entry(xfer, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool last_xfer = list_is_last(&xfer->transfer_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &msg->transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) status = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) total_len += r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msg->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) msg->actual_length = total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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