^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011, 2012 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "spi-cavium.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int octeon_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct octeon_spi *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) p = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (IS_ERR(reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) err = PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) p->register_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) p->sys_freq = octeon_get_io_clock_rate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) p->regs.config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) p->regs.status = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) p->regs.tx = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) p->regs.data = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) master->mode_bits = SPI_CPHA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SPI_CPOL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SPI_CS_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SPI_LSB_FIRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) master->transfer_one_message = octeon_spi_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) err = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(&pdev->dev, "register master failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int octeon_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct octeon_spi *p = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Clear the CSENA* and put everything in a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writeq(0, p->register_base + OCTEON_SPI_CFG(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct of_device_id octeon_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .compatible = "cavium,octeon-3010-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_DEVICE_TABLE(of, octeon_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct platform_driver octeon_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "spi-octeon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .of_match_table = octeon_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .probe = octeon_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .remove = octeon_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) module_platform_driver(octeon_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_AUTHOR("David Daney");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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