^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence SPI controller driver (master mode only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Name of this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CDNS_SPI_NAME "cdns-spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Register offset definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CDNS_SPI_DR 0x18 /* Delay Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPI_AUTOSUSPEND_TIMEOUT 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * SPI Configuration Register bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This register contains various control bits that affect the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * of the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CDNS_SPI_CR_SSCTRL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CDNS_SPI_CR_SSFORCE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CDNS_SPI_CR_BAUD_DIV_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SPI Configuration Register - Baud rate and slave select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * These are the values used in the calculation of baud rate divisor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * setting the slave select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CDNS_SPI_SS0 0x1 /* Slave Select zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * SPI Interrupt Registers bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CDNS_SPI_IXR_MODF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * SPI Enable Register bit Masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This register is used to enable or disable the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* SPI FIFO depth in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CDNS_SPI_FIFO_DEPTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Default number of chip select lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CDNS_SPI_DEFAULT_NUM_CS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * struct cdns_spi - This definition defines spi driver instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @regs: Virtual address of the SPI controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @ref_clk: Pointer to the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @pclk: Pointer to the APB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @speed_hz: Current SPI bus clock speed in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @txbuf: Pointer to the TX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @rxbuf: Pointer to the RX buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @tx_bytes: Number of bytes left to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @rx_bytes: Number of bytes requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @dev_busy: Device busy flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @is_decoded_cs: Flag for decoder property set or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct cdns_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const u8 *txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 *rxbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 dev_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 is_decoded_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Macros for the SPI controller read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return readl_relaxed(xspi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel_relaxed(val, xspi->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @xspi: Pointer to the cdns_spi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * On reset the SPI controller is configured to be in master mode, baud rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * to 1 and size of the word to be transferred as 8 bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * This function initializes the SPI controller to disable and clear all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * interrupts, enable manual slave select and manual start, deselect all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * chip select lines, and enable the SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void cdns_spi_init_hw(struct cdns_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (xspi->is_decoded_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Clear the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cdns_spi_read(xspi, CDNS_SPI_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * cdns_spi_chipselect - Select or deselect the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @is_high: Select(0) or deselect (1) the chip select line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (is_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Deselect the slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ctrl_reg |= CDNS_SPI_CR_SSCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Select the slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!(xspi->is_decoded_cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CDNS_SPI_SS_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CDNS_SPI_CR_SSCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CDNS_SPI_CR_SSCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * cdns_spi_config_clock_mode - Sets clock polarity and phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Sets the requested clock polarity and phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void cdns_spi_config_clock_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 ctrl_reg, new_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ctrl_reg = new_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Set the SPI clock phase and clock polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) new_ctrl_reg |= CDNS_SPI_CR_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) new_ctrl_reg |= CDNS_SPI_CR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (new_ctrl_reg != ctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Just writing the CR register does not seem to apply the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * setting changes. This is problematic when changing the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * polarity as it will cause the SPI slave to see spurious clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * transitions. To workaround the issue toggle the ER register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * cdns_spi_config_clock_freq - Sets clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @transfer: Pointer to the spi_transfer structure which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * information about next transfer setup parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Sets the requested clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Note: If the requested frequency is not an exact match with what can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * obtained using the prescalar value the driver sets the clock frequency which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * is lower than the requested frequency (maximum lower) for the transfer. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * the requested frequency is higher or lower than that is supported by the SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * controller the driver will set the highest or lowest frequency supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void cdns_spi_config_clock_freq(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 ctrl_reg, baud_rate_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) frequency = xspi->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Set the clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (xspi->speed_hz != transfer->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* first valid value is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) baud_rate_val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) xspi->speed_hz = frequency / (2 << baud_rate_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @transfer: Pointer to the spi_transfer structure which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * information about next transfer setup parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Sets the operational mode of SPI controller for the next SPI transfer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * sets the requested clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Return: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int cdns_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cdns_spi_config_clock_freq(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __func__, spi->mode, spi->bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) xspi->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @xspi: Pointer to the cdns_spi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long trans_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (xspi->tx_bytes > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* When xspi in busy condition, bytes may send failed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * then spi control did't work thoroughly, add one byte delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CDNS_SPI_IXR_TXFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (xspi->txbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) xspi->tx_bytes--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) trans_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * cdns_spi_irq - Interrupt service routine of the SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @dev_id: Pointer to the xspi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * This function handles TX empty and Mode Fault interrupts only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * On TX empty interrupt this function reads the received data from RX FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * fills the TX FIFO if there is any data remaining to be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * On Mode Fault interrupt this function indicates that transfer is completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * the SPI subsystem will identify the error as the remaining bytes to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * transferred is non-zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 intr_status, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) status = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (intr_status & CDNS_SPI_IXR_MODF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Indicate that transfer is completed, the SPI subsystem will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * identify the error as the remaining bytes to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * transferred is non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else if (intr_status & CDNS_SPI_IXR_TXOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned long trans_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Read out the data from the RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) while (trans_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) data = cdns_spi_read(xspi, CDNS_SPI_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (xspi->rxbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *xspi->rxbuf++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) xspi->rx_bytes--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) trans_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (xspi->tx_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* There is more data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cdns_spi_fill_tx_fifo(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Transfer is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cdns_spi_write(xspi, CDNS_SPI_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CDNS_SPI_IXR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int cdns_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cdns_spi_config_clock_mode(msg->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * cdns_transfer_one - Initiates the SPI transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @master: Pointer to spi_master structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @spi: Pointer to the spi_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * @transfer: Pointer to the spi_transfer structure which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * information about next transfer parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * This function fills the TX FIFO, starts the SPI transfer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * returns a positive transfer count so that core will wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Return: Number of bytes transferred in the last transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int cdns_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) xspi->txbuf = transfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) xspi->rxbuf = transfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) xspi->tx_bytes = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) xspi->rx_bytes = transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cdns_spi_setup_transfer(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cdns_spi_fill_tx_fifo(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spi_transfer_delay_exec(transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return transfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @master: Pointer to the spi_master structure which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * information about the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * This function enables SPI master controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int cdns_prepare_transfer_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @master: Pointer to the spi_master structure which provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * information about the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * This function disables the SPI master controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int cdns_unprepare_transfer_hardware(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * cdns_spi_probe - Probe method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * This function initializes the driver data structures and the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int cdns_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct cdns_spi *xspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) xspi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (IS_ERR(xspi->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = PTR_ERR(xspi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (IS_ERR(xspi->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev, "pclk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = PTR_ERR(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (IS_ERR(xspi->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(&pdev->dev, "ref_clk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = PTR_ERR(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = clk_prepare_enable(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(&pdev->dev, "Unable to enable APB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto remove_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = clk_prepare_enable(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(&pdev->dev, "Unable to enable device clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto clk_dis_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &xspi->is_decoded_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) xspi->is_decoded_cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* SPI controller initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cdns_spi_init_hw(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0, pdev->name, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&pdev->dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) master->prepare_message = cdns_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) master->transfer_one = cdns_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) master->set_cs = cdns_spi_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) xspi->clk_rate = clk_get_rate(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Set to default valid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) master->max_speed_hz = xspi->clk_rate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) xspi->speed_hz = master->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(&pdev->dev, "spi_register_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto clk_dis_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_dis_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_disable_unprepare(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clk_dis_apb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk_disable_unprepare(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) remove_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * cdns_spi_remove - Remove method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @pdev: Pointer to the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * This function is called if a device is physically removed from the system or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * if the driver module is being unloaded. It frees all resources allocated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int cdns_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_disable_unprepare(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clk_disable_unprepare(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * cdns_spi_suspend - Suspend method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * This function disables the SPI controller and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * changes the driver state to "suspend"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int __maybe_unused cdns_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * cdns_spi_resume - Resume method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * This function changes the driver state to "ready"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int __maybe_unused cdns_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cdns_spi_init_hw(xspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * This function enables the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int __maybe_unused cnds_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = clk_prepare_enable(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(dev, "Cannot enable APB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = clk_prepare_enable(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_err(dev, "Cannot enable device clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) clk_disable_unprepare(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * @dev: Address of the platform_device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * This function disables the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * Return: Always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int __maybe_unused cnds_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct cdns_spi *xspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) clk_disable_unprepare(xspi->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) clk_disable_unprepare(xspi->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cnds_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const struct of_device_id cdns_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { .compatible = "xlnx,zynq-spi-r1p6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { .compatible = "cdns,spi-r1p6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static struct platform_driver cdns_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .probe = cdns_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .remove = cdns_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .name = CDNS_SPI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .of_match_table = cdns_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .pm = &cdns_spi_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) module_platform_driver(cdns_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MODULE_DESCRIPTION("Cadence SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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