^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Driver for Cadence QSPI Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CQSPI_NAME "cadence-qspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CQSPI_MAX_CHIPSELECT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CQSPI_NEEDS_WR_DELAY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CQSPI_DISABLE_DAC_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CQSPI_SUPPORTS_OCTAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct cqspi_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct cqspi_flash_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct cqspi_st *cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 read_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 tshsl_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 tsd2d_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 tchsh_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 tslch_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 inst_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct cqspi_st {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *ahb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) resource_size_t ahb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct completion transfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct completion rx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dma_addr_t mmap_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int current_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long master_ref_clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool is_decoded_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 fifo_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool rclk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 trigger_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 wr_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool use_direct_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct cqspi_driver_platdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 hwcaps_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Operation timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CQSPI_TIMEOUT_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CQSPI_READ_TIMEOUT_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Instruction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CQSPI_INST_TYPE_SINGLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CQSPI_INST_TYPE_DUAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CQSPI_INST_TYPE_QUAD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CQSPI_INST_TYPE_OCTAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CQSPI_DUMMY_CLKS_PER_BYTE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CQSPI_DUMMY_BYTES_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CQSPI_DUMMY_CLKS_MAX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CQSPI_STIG_DATA_LEN_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CQSPI_REG_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CQSPI_REG_CONFIG_BAUD_LSB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CQSPI_REG_CONFIG_IDLE_LSB 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CQSPI_REG_RD_INSTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CQSPI_REG_WR_INSTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CQSPI_REG_DELAY 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CQSPI_REG_DELAY_TSLCH_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CQSPI_REG_DELAY_TCHSH_LSB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CQSPI_REG_DELAY_TSD2D_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CQSPI_REG_DELAY_TSHSL_LSB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CQSPI_REG_READCAPTURE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CQSPI_REG_SIZE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CQSPI_REG_SIZE_ADDRESS_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CQSPI_REG_SIZE_PAGE_LSB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CQSPI_REG_SIZE_BLOCK_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CQSPI_REG_SRAMPARTITION 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CQSPI_REG_INDIRECTTRIGGER 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CQSPI_REG_DMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CQSPI_REG_DMA_SINGLE_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CQSPI_REG_DMA_BURST_LSB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CQSPI_REG_DMA_BURST_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CQSPI_REG_REMAP 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CQSPI_REG_MODE_BIT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CQSPI_REG_SDRAMLEVEL 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CQSPI_REG_IRQSTATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CQSPI_REG_IRQMASK 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CQSPI_REG_INDIRECTRD 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CQSPI_REG_INDIRECTRDBYTES 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CQSPI_REG_CMDCTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CQSPI_REG_INDIRECTWR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CQSPI_REG_INDIRECTWRBYTES 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CQSPI_REG_CMDADDRESS 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CQSPI_REG_CMDREADDATALOWER 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CQSPI_REG_CMDREADDATAUPPER 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Interrupt status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CQSPI_REG_IRQ_IND_COMP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CQSPI_REG_IRQ_WATERMARK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CQSPI_REG_IRQ_IND_SRAM_FULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CQSPI_REG_IRQ_IND_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CQSPI_REG_IRQ_WATERMARK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CQSPI_REG_IRQ_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return readl_relaxed_poll_timeout(reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (((clr ? ~val : val) & mask) == mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 10, CQSPI_TIMEOUT_MS * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool cqspi_is_idle(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct cqspi_st *cqspi = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Read interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) complete(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 rdreg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int cqspi_wait_idle(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const unsigned int poll_idle_retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Read few times in succession to ensure the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * is indeed idle, that is, the bit does not transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * low again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (cqspi_is_idle(cqspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (count >= poll_idle_retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Timeout, in busy mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&cqspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "QSPI is still busy after %dms timeout.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CQSPI_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Write the CMDCTRL without start execution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel(reg, reg_base + CQSPI_REG_CMDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Start execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel(reg, reg_base + CQSPI_REG_CMDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Polling for completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(&cqspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Flash command execution timed out.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Polling QSPI idle status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return cqspi_wait_idle(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 *rxbuf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 opcode = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) size_t n_rx = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) size_t read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(&cqspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "Invalid input argument, len %zu rxbuf 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) n_rx, rxbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rdreg = cqspi_calc_rdreg(f_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* 0 means 1 byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) status = cqspi_exec_flash_cmd(cqspi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Put the read value into rx_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) read_len = (n_rx > 4) ? 4 : n_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) memcpy(rxbuf, ®, read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rxbuf += read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (n_rx > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) read_len = n_rx - read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) memcpy(rxbuf, ®, read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const u8 opcode = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const u8 *txbuf = op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) size_t n_tx = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) size_t write_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(&cqspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) n_tx, txbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) reg |= ((op->addr.nbytes - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (n_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) write_len = (n_tx > 4) ? 4 : n_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) memcpy(&data, txbuf, write_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) txbuf += write_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (n_tx > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) write_len = n_tx - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) memcpy(&data, txbuf, write_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return cqspi_exec_flash_cmd(cqspi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int dummy_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reg |= cqspi_calc_rdreg(f_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Setup dummy clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dummy_clk = op->dummy.nbytes * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dummy_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) << CQSPI_REG_RD_INSTR_DUMMY_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writel(reg, reg_base + CQSPI_REG_RD_INSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Set address width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reg = readl(reg_base + CQSPI_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) reg |= (op->addr.nbytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writel(reg, reg_base + CQSPI_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 *rxbuf, loff_t from_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const size_t n_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct device *dev = &cqspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void __iomem *ahb_base = cqspi->ahb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int remaining = n_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int mod_bytes = n_rx % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int bytes_to_read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 *rxbuf_end = rxbuf + n_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Clear all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) reinit_completion(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel(CQSPI_REG_INDIRECTRD_START_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) reg_base + CQSPI_REG_INDIRECTRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) while (remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!wait_for_completion_timeout(&cqspi->transfer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bytes_to_read = cqspi_get_rd_sram_level(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (ret && bytes_to_read == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "Indirect read timeout, no bytes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto failrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) while (bytes_to_read != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int word_remain = round_down(remaining, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bytes_to_read *= cqspi->fifo_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bytes_to_read = bytes_to_read > remaining ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) remaining : bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bytes_to_read = round_down(bytes_to_read, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Read 4 byte word chunks then single bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (bytes_to_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ioread32_rep(ahb_base, rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) (bytes_to_read / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else if (!word_remain && mod_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned int temp = ioread32(ahb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bytes_to_read = mod_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) memcpy(rxbuf, &temp, min((unsigned int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (rxbuf_end - rxbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bytes_to_read));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rxbuf += bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) remaining -= bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bytes_to_read = cqspi_get_rd_sram_level(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (remaining > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) reinit_completion(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Check indirect done status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(dev, "Indirect read completion error (%i)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) goto failrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(0, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Clear indirect completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) failrd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel(0, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Cancel the indirect read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg_base + CQSPI_REG_INDIRECTRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Set opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(reg, reg_base + CQSPI_REG_WR_INSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) reg = cqspi_calc_rdreg(f_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writel(reg, reg_base + CQSPI_REG_RD_INSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) reg = readl(reg_base + CQSPI_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reg |= (op->addr.nbytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writel(reg, reg_base + CQSPI_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) loff_t to_addr, const u8 *txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const size_t n_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct device *dev = &cqspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned int remaining = n_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int write_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Clear all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) reinit_completion(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) writel(CQSPI_REG_INDIRECTWR_START_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) reg_base + CQSPI_REG_INDIRECTWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Controller programming sequence, couple of cycles of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * QSPI_REF_CLK delay is required for the above bit to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * be internally synchronized by the QSPI module. Provide 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * cycles of delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (cqspi->wr_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ndelay(cqspi->wr_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) while (remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) size_t write_words, mod_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) write_bytes = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) write_words = write_bytes / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mod_bytes = write_bytes % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Write 4 bytes at a time then single bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (write_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) txbuf += (write_words * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (mod_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int temp = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) memcpy(&temp, txbuf, mod_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) iowrite32(temp, cqspi->ahb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) txbuf += mod_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!wait_for_completion_timeout(&cqspi->transfer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(dev, "Indirect write timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto failwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) remaining -= write_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (remaining > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) reinit_completion(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Check indirect done status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(dev, "Indirect write completion error (%i)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto failwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Disable interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel(0, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Clear indirect completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) cqspi_wait_idle(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) failwr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Disable interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(0, reg_base + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Cancel the indirect write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg_base + CQSPI_REG_INDIRECTWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int chip_select = f_pdata->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) reg = readl(reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (cqspi->is_decoded_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reg |= CQSPI_REG_CONFIG_DECODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Convert CS if without decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * CS0 to 4b'1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * CS1 to 4b'1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * CS2 to 4b'1011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * CS3 to 4b'0111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) chip_select = 0xF & ~(1 << chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(reg, reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) const unsigned int ns_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ticks = ref_clk_hz / 1000; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) void __iomem *iobase = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int tshsl, tchsh, tslch, tsd2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned int tsclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* calculate the number of ref ticks for one sclk tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* this particular value must be at least one sclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (tshsl < tsclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) tshsl = tsclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) << CQSPI_REG_DELAY_TSHSL_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) << CQSPI_REG_DELAY_TCHSH_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) << CQSPI_REG_DELAY_TSLCH_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) << CQSPI_REG_DELAY_TSD2D_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) writel(reg, iobase + CQSPI_REG_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 reg, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Recalculate the baudrate divisor based on QSPI specification. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) reg = readl(reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) writel(reg, reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void cqspi_readdata_capture(struct cqspi_st *cqspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) const bool bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) const unsigned int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) reg = readl(reg_base + CQSPI_REG_READCAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) << CQSPI_REG_READCAPTURE_DELAY_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) << CQSPI_REG_READCAPTURE_DELAY_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel(reg, reg_base + CQSPI_REG_READCAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) void __iomem *reg_base = cqspi->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) reg = readl(reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) writel(reg, reg_base + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned long sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int switch_cs = (cqspi->current_cs != f_pdata->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int switch_ck = (cqspi->sclk != sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (switch_cs || switch_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) cqspi_controller_enable(cqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Switch chip select. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (switch_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) cqspi->current_cs = f_pdata->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cqspi_chipselect(f_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Setup baudrate divisor and delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (switch_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cqspi->sclk = sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) cqspi_config_baudrate_div(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) cqspi_delay(f_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) f_pdata->read_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (switch_cs || switch_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) cqspi_controller_enable(cqspi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (op->data.dir == SPI_MEM_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) switch (op->data.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) loff_t to = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) size_t len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const u_char *buf = op->data.buf.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = cqspi_set_protocol(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = cqspi_write_setup(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) memcpy_toio(cqspi->ahb_base + to, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return cqspi_wait_idle(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return cqspi_indirect_write_execute(f_pdata, to, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static void cqspi_rx_dma_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct cqspi_st *cqspi = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) complete(&cqspi->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u_char *buf, loff_t from, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct device *dev = &cqspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dma_addr_t dma_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct device *ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) memcpy_fromio(buf, cqspi->ahb_base + from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ddev = cqspi->rx_chan->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (dma_mapping_error(ddev, dma_dst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(dev, "dma mapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(dev, "device_prep_dma_memcpy error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) tx->callback = cqspi_rx_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) tx->callback_param = cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cookie = tx->tx_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) reinit_completion(&cqspi->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_err(dev, "dma_submit_error %d\n", cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dma_async_issue_pending(cqspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) msecs_to_jiffies(len))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dmaengine_terminate_sync(cqspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(dev, "DMA wait_for_completion_timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct cqspi_st *cqspi = f_pdata->cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) loff_t from = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) size_t len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u_char *buf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = cqspi_set_protocol(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = cqspi_read_setup(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return cqspi_direct_read_execute(f_pdata, buf, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return cqspi_indirect_read_execute(f_pdata, buf, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct cqspi_flash_pdata *f_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cqspi_configure(f_pdata, mem->spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return cqspi_command_read(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return cqspi_read(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (!op->addr.nbytes || !op->data.buf.out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return cqspi_command_write(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return cqspi_write(f_pdata, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = cqspi_mem_process(mem, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct cqspi_flash_pdata *f_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_err(&pdev->dev, "couldn't determine read-delay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct device *dev = &cqspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dev_err(dev, "couldn't determine fifo-depth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev_err(dev, "couldn't determine fifo-width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (of_property_read_u32(np, "cdns,trigger-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) &cqspi->trigger_address)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(dev, "couldn't determine trigger-address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void cqspi_controller_init(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cqspi_controller_enable(cqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* Configure the remap address register, no remap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) writel(0, cqspi->iobase + CQSPI_REG_REMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Disable all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Configure the SRAM split to 1:1 . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* Load indirect trigger address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) writel(cqspi->trigger_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Program read watermark -- 1/2 of the FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Program write watermark -- 1/8 of the FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Enable Direct Access Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) cqspi_controller_enable(cqspi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dma_cap_set(DMA_MEMCPY, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) cqspi->rx_chan = dma_request_chan_by_mask(&mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (IS_ERR(cqspi->rx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret = PTR_ERR(cqspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) cqspi->rx_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) init_completion(&cqspi->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const char *cqspi_get_name(struct spi_mem *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct device *dev = &cqspi->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const struct spi_controller_mem_ops cqspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .exec_op = cqspi_exec_mem_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .get_name = cqspi_get_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int cqspi_setup_flash(struct cqspi_st *cqspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct platform_device *pdev = cqspi->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct cqspi_flash_pdata *f_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Get flash device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) for_each_available_child_of_node(dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = of_property_read_u32(np, "reg", &cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev_err(dev, "Couldn't determine chip select.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (cs >= CQSPI_MAX_CHIPSELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_err(dev, "Chip select %d out of range.\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) f_pdata = &cqspi->f_pdata[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) f_pdata->cqspi = cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) f_pdata->cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static int cqspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) const struct cqspi_driver_platdata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct reset_control *rstc, *rstc_ocp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct resource *res_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct cqspi_st *cqspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_err(&pdev->dev, "spi_alloc_master failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) master->mem_ops = &cqspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) cqspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cqspi->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) platform_set_drvdata(pdev, cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Obtain configuration from OF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = cqspi_of_get_pdata(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dev_err(dev, "Cannot get mandatory OF data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Obtain QSPI clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) cqspi->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(cqspi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(dev, "Cannot claim QSPI clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ret = PTR_ERR(cqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Obtain and remap controller address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) cqspi->iobase = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (IS_ERR(cqspi->iobase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_err(dev, "Cannot remap controller address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = PTR_ERR(cqspi->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Obtain and remap AHB address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (IS_ERR(cqspi->ahb_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dev_err(dev, "Cannot remap AHB address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ret = PTR_ERR(cqspi->ahb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) cqspi->ahb_size = resource_size(res_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) init_completion(&cqspi->transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Obtain IRQ line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) goto probe_master_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = clk_prepare_enable(cqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dev_err(dev, "Cannot enable QSPI clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto probe_clk_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Obtain QSPI reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dev_err(dev, "Cannot get QSPI reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto probe_reset_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (IS_ERR(rstc_ocp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ret = PTR_ERR(rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(dev, "Cannot get QSPI OCP reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) goto probe_reset_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) reset_control_assert(rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) reset_control_deassert(rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ddata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (ddata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) cqspi->master_ref_clk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) master->mode_bits |= SPI_RX_OCTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) cqspi->use_direct_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pdev->name, cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_err(dev, "Cannot request IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto probe_reset_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) cqspi_wait_idle(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) cqspi_controller_init(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) cqspi->current_cs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) cqspi->sclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = cqspi_setup_flash(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_err(dev, "failed to setup flash parameters %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) goto probe_setup_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (cqspi->use_direct_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = cqspi_request_mmap_dma(cqspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) goto probe_setup_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto probe_setup_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) probe_setup_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) cqspi_controller_enable(cqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) probe_reset_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) clk_disable_unprepare(cqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) probe_clk_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) probe_master_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int cqspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct cqspi_st *cqspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) cqspi_controller_enable(cqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (cqspi->rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dma_release_channel(cqspi->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) clk_disable_unprepare(cqspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int cqspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct cqspi_st *cqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) cqspi_controller_enable(cqspi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static int cqspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct cqspi_st *cqspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) cqspi_controller_enable(cqspi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static const struct dev_pm_ops cqspi__dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .suspend = cqspi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .resume = cqspi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define CQSPI_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const struct cqspi_driver_platdata cdns_qspi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .quirks = CQSPI_DISABLE_DAC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static const struct cqspi_driver_platdata k2g_qspi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .quirks = CQSPI_NEEDS_WR_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const struct cqspi_driver_platdata am654_ospi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .quirks = CQSPI_NEEDS_WR_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const struct of_device_id cqspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .compatible = "cdns,qspi-nor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .data = &cdns_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .compatible = "ti,k2g-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .data = &k2g_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .compatible = "ti,am654-ospi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .data = &am654_ospi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static struct platform_driver cqspi_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .probe = cqspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .remove = cqspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .name = CQSPI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .pm = CQSPI_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .of_match_table = cqspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) module_platform_driver(cqspi_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) MODULE_ALIAS("platform:" CQSPI_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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