Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * polling/bitbanging SPI master controller driver utilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi_bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SPI_BITBANG_CS_DELAY	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Use this for GPIO or shift-register level hardware APIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * to glue code.  These bitbang setup() and cleanup() routines are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * used, though maybe they're called from controller-aware code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * chipselect() and friends may use spi_device->controller_data and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * controller registers as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * NOTE:  SPI controller pins can often be used as GPIO pins instead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * which means you could use a bitbang driver either to get hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * working quickly, or testing for differences that aren't speed related.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct spi_bitbang_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned	nsecs;	/* (clock cycle time)/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 					u32 word, u8 bits, unsigned flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned	(*txrx_bufs)(struct spi_device *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 					u32 (*txrx_word)(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 						struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 						unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 						u32 word, u8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 						unsigned flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					unsigned, struct spi_transfer *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					unsigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static unsigned bitbang_txrx_8(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct spi_device	*spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32			(*txrx_word)(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					u32 word, u8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 					unsigned flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned		ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct spi_transfer	*t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned		bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned		count = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	const u8		*tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8			*rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	while (likely(count > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		u8		word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			word = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		word = txrx_word(spi, ns, word, bits, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			*rx++ = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		count -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return t->len - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static unsigned bitbang_txrx_16(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct spi_device	*spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32			(*txrx_word)(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					u32 word, u8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					unsigned flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned		ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct spi_transfer	*t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned		bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned		count = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	const u16		*tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u16			*rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	while (likely(count > 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		u16		word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			word = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		word = txrx_word(spi, ns, word, bits, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			*rx++ = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return t->len - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned bitbang_txrx_32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct spi_device	*spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32			(*txrx_word)(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					unsigned nsecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					u32 word, u8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					unsigned flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned		ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct spi_transfer	*t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned		bits = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned		count = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	const u32		*tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32			*rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	while (likely(count > 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		u32		word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			word = *tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		word = txrx_word(spi, ns, word, bits, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			*rx++ = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		count -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return t->len - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct spi_bitbang_cs	*cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8			bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32			hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		bits_per_word = t->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		hz = t->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		bits_per_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* spi_transfer level calls that work per-word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (bits_per_word <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		cs->txrx_bufs = bitbang_txrx_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	else if (bits_per_word <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		cs->txrx_bufs = bitbang_txrx_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	else if (bits_per_word <= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		cs->txrx_bufs = bitbang_txrx_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* nsecs = (clock period)/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (!hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		cs->nsecs = (1000000000/2) / hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * spi_bitbang_setup - default setup for per-word I/O loops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int spi_bitbang_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct spi_bitbang_cs	*cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct spi_bitbang	*bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bool			initial_setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int			retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	bitbang = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (!cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		spi->controller_state = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		initial_setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* per-word shift register access, in hardware or bitbanging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!cs->txrx_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (bitbang->setup_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		retval = bitbang->setup_transfer(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		kfree(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXPORT_SYMBOL_GPL(spi_bitbang_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * spi_bitbang_cleanup - default cleanup for per-word I/O loops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void spi_bitbang_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	kfree(spi->controller_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct spi_bitbang_cs	*cs = spi->controller_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned		nsecs = cs->nsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct spi_bitbang	*bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	bitbang = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (bitbang->set_line_direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		err = bitbang->set_line_direction(spi, !!(t->tx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (spi->mode & SPI_3WIRE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		unsigned flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		flags = t->tx_buf ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * SECOND PART ... simple transfer queue runner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * This costs a task context per controller, running the queue by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * performing each transfer in sequence.  Smarter hardware can queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * several DMA transfers at once, and process several controller queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * in parallel; this driver doesn't match such hardware very well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Drivers can provide word-at-a-time i/o primitives, or provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * transfer-at-a-time ones to leverage dma or fifo hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int spi_bitbang_prepare_hardware(struct spi_master *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct spi_bitbang	*bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	bitbang = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	mutex_lock(&bitbang->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	bitbang->busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	mutex_unlock(&bitbang->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int spi_bitbang_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				    struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				    struct spi_transfer *transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct spi_bitbang *bitbang = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (bitbang->setup_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		status = bitbang->setup_transfer(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (transfer->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		status = bitbang->txrx_bufs(spi, transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (status == transfer->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	else if (status >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		status = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct spi_bitbang	*bitbang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	bitbang = spi_master_get_devdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mutex_lock(&bitbang->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	bitbang->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mutex_unlock(&bitbang->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void spi_bitbang_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* SPI core provides CS high / low, but bitbang driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 * expects CS active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 * spi device driver takes care of handling SPI_CS_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ndelay(SPI_BITBANG_CS_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	bitbang->chipselect(spi, enable ? BITBANG_CS_ACTIVE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			    BITBANG_CS_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ndelay(SPI_BITBANG_CS_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int spi_bitbang_init(struct spi_bitbang *bitbang)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct spi_master *master = bitbang->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	bool custom_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	 * We only need the chipselect callback if we are actually using it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 * If we just use GPIO descriptors, it is surplus. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 * SPI_MASTER_GPIO_SS flag is set, we always need to call the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	 * driver-specific chipselect routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	custom_cs = (!master->use_gpio_descriptors ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		     (master->flags & SPI_MASTER_GPIO_SS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (custom_cs && !bitbang->chipselect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	mutex_init(&bitbang->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (!master->mode_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (master->transfer || master->transfer_one_message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	master->transfer_one = spi_bitbang_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * When using GPIO descriptors, the ->set_cs() callback doesn't even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 * get called unless SPI_MASTER_GPIO_SS is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (custom_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		master->set_cs = spi_bitbang_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (!bitbang->txrx_bufs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		bitbang->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		bitbang->txrx_bufs = spi_bitbang_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		if (!master->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			if (!bitbang->setup_transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 				bitbang->setup_transfer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 					 spi_bitbang_setup_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			master->setup = spi_bitbang_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			master->cleanup = spi_bitbang_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) EXPORT_SYMBOL_GPL(spi_bitbang_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)  * spi_bitbang_start - start up a polled/bitbanging SPI master driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)  * @bitbang: driver handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)  * Caller should have zero-initialized all parts of the structure, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  * provided callbacks for chip selection and I/O loops.  If the master has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  * a transfer method, its final step should call spi_bitbang_transfer; or,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  * that's the default if the transfer routine is not initialized.  It should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * also set up the bus number and number of chipselects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  * For i/o loops, provide callbacks either per-word (for bitbanging, or for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)  * hardware that basically exposes a shift register) or per-spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)  * (which takes better advantage of hardware like fifos or DMA engines).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)  * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)  * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)  * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)  * routine isn't initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)  * This routine registers the spi_master, which will process requests in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)  * dedicated task, keeping IRQs unblocked most of the time.  To stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  * processing those requests, call spi_bitbang_stop().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)  * On success, this routine will take a reference to master. The caller is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)  * responsible for calling spi_bitbang_stop() to decrement the reference and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)  * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)  * leak.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int spi_bitbang_start(struct spi_bitbang *bitbang)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct spi_master *master = bitbang->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	ret = spi_bitbang_init(bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	/* driver may get busy before register() returns, especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 * if someone registered boardinfo for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	ret = spi_register_master(spi_master_get(master));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) EXPORT_SYMBOL_GPL(spi_bitbang_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)  * spi_bitbang_stop - stops the task providing spi communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) void spi_bitbang_stop(struct spi_bitbang *bitbang)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	spi_unregister_master(bitbang->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) EXPORT_SYMBOL_GPL(spi_bitbang_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)