^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom BCM63xx SPI controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* BCM 6338/6348 SPI core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPI_6348_RSET_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPI_6348_CMD 0x00 /* 16-bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPI_6348_INT_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPI_6348_INT_MASK_ST 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPI_6348_INT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPI_6348_ST 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_6348_CLK_CFG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_6348_FILL_BYTE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_6348_MSG_TAIL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPI_6348_RX_TAIL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_6348_MSG_CTL_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_6348_MSG_DATA 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_6348_MSG_DATA_SIZE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPI_6348_RX_DATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_6348_RX_DATA_SIZE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* BCM 3368/6358/6262/6368 SPI core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_6358_RSET_SIZE 1804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_6358_MSG_CTL_WIDTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_6358_MSG_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_6358_MSG_DATA_SIZE 0x21e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPI_6358_RX_DATA 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_6358_RX_DATA_SIZE 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_6358_CMD 0x700 /* 16-bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPI_6358_INT_STATUS 0x702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPI_6358_INT_MASK_ST 0x703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPI_6358_INT_MASK 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPI_6358_ST 0x705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_6358_CLK_CFG 0x706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPI_6358_FILL_BYTE 0x707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPI_6358_MSG_TAIL 0x709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_6358_RX_TAIL 0x70B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Shared SPI definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Message configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPI_FD_RW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPI_HD_W 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPI_HD_R 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_BYTE_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPI_6348_MSG_TYPE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPI_6358_MSG_TYPE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPI_CMD_NOOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI_CMD_SOFT_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPI_CMD_HARD_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPI_CMD_START_IMMEDIATE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPI_CMD_COMMAND_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPI_CMD_COMMAND_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPI_CMD_DEVICE_ID_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPI_CMD_ONE_BYTE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPI_CMD_ONE_WIRE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPI_DEV_ID_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPI_DEV_ID_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPI_DEV_ID_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPI_DEV_ID_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPI_INTR_CMD_DONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPI_INTR_RX_OVERFLOW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPI_INTR_TX_UNDERFLOW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPI_INTR_TX_OVERFLOW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPI_INTR_RX_UNDERFLOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPI_INTR_CLEAR_ALL 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPI_RX_EMPTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPI_CMD_BUSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPI_SERIAL_BUSY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPI_CLK_20MHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPI_CLK_0_391MHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPI_CLK_0_781MHZ 0x02 /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPI_CLK_1_563MHZ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPI_CLK_3_125MHZ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPI_CLK_6_250MHZ 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPI_CLK_12_50MHZ 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPI_CLK_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPI_SSOFFTIME_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPI_SSOFFTIME_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPI_BYTE_SWAP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum bcm63xx_regs_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SPI_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SPI_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SPI_INT_MASK_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SPI_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SPI_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SPI_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SPI_FILL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SPI_MSG_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SPI_RX_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SPI_MSG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SPI_MSG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SPI_RX_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SPI_MSG_TYPE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SPI_MSG_CTL_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SPI_MSG_DATA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCM63XX_SPI_MAX_PREPEND 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BCM63XX_SPI_MAX_CS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BCM63XX_SPI_BUS_NUM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct bcm63xx_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const unsigned long *reg_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int msg_type_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int msg_ctl_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* data iomem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 __iomem *tx_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const u8 __iomem *rx_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return readb(bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ioread16be(bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return readw(bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writeb(value, bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writew(value, bs->regs + bs->reg_offsets[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 20000000, SPI_CLK_20MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 12500000, SPI_CLK_12_50MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 6250000, SPI_CLK_6_250MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 3125000, SPI_CLK_3_125MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 1563000, SPI_CLK_1_563MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 781000, SPI_CLK_0_781MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 391000, SPI_CLK_0_391MHZ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 clk_cfg, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Default to lowest clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_cfg = SPI_CLK_0_391MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Find the closest clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (i = 0; i < SPI_CLK_MASK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_cfg = bcm63xx_spi_freq_table[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* clear existing clock configuration bits of the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg = bcm_spi_readb(bs, SPI_CLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg &= ~SPI_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) reg |= clk_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk_cfg, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* the spi->mode bits understood by this driver: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MODEBITS (SPI_CPOL | SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int num_transfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 msg_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int i, timeout = 0, prepend_len = 0, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct spi_transfer *t = first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bool do_rx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bool do_tx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Disable the CMD_DONE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bcm_spi_writeb(bs, 0, SPI_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) t->tx_buf, t->rx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) prepend_len = t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* prepare the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < num_transfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) do_tx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* don't prepend more than one tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (t != first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) prepend_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) do_rx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* prepend is half-duplex write only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (t == first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) prepend_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) len += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) t = list_entry(t->transfer_list.next, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reinit_completion(&bs->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Fill in the Message control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (do_rx && do_tx && prepend_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else if (do_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else if (do_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) switch (bs->msg_ctl_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Issue the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cmd = SPI_CMD_START_IMMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bcm_spi_writew(bs, cmd, SPI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Enable the CMD_DONE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) timeout = wait_for_completion_timeout(&bs->done, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!do_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) t = first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Read out all the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; i < num_transfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (t->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (t != first || prepend_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) len += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) t = list_entry(t->transfer_list.next, struct spi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int bcm63xx_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct bcm63xx_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct spi_transfer *t, *first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int n_transfers = 0, total_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bool can_use_prepend = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * This SPI controller does not support keeping CS active after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Work around this by merging as many transfers we can into one big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * full-duplex transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) first = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) n_transfers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) total_len += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) first->len <= BCM63XX_SPI_MAX_PREPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) can_use_prepend = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else if (can_use_prepend && t->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) can_use_prepend = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* we can only transfer one fifo worth of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if ((can_use_prepend &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (!can_use_prepend && total_len > bs->fifo_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) total_len, bs->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* all combined transfers have to have the same speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (t->speed_hz != first->speed_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(&spi->dev, "unable to change speed between transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* CS will be deasserted directly after transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (t->delay_usecs || t->delay.value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (t->cs_change ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) list_is_last(&t->transfer_list, &m->transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* configure adapter for a new transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bcm63xx_spi_setup_transfer(spi, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* send the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) status = bcm63xx_txrx_bufs(spi, first, n_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) m->actual_length += total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) n_transfers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) total_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) can_use_prepend = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) m->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* This driver supports single master mode only. Hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * CMD_DONE is the only interrupt we care about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct spi_master *master = (struct spi_master *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct bcm63xx_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Read interupts and clear them immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) intr = bcm_spi_readb(bs, SPI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bcm_spi_writeb(bs, 0, SPI_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* A transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (intr & SPI_INTR_CMD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) complete(&bs->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static size_t bcm63xx_spi_max_length(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return bs->fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const unsigned long bcm6348_spi_reg_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [SPI_CMD] = SPI_6348_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [SPI_INT_STATUS] = SPI_6348_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [SPI_INT_MASK] = SPI_6348_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [SPI_ST] = SPI_6348_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [SPI_CLK_CFG] = SPI_6348_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [SPI_RX_TAIL] = SPI_6348_RX_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [SPI_MSG_CTL] = SPI_6348_MSG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [SPI_MSG_DATA] = SPI_6348_MSG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [SPI_RX_DATA] = SPI_6348_RX_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const unsigned long bcm6358_spi_reg_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [SPI_CMD] = SPI_6358_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [SPI_INT_STATUS] = SPI_6358_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [SPI_INT_MASK] = SPI_6358_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [SPI_ST] = SPI_6358_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [SPI_CLK_CFG] = SPI_6358_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [SPI_RX_TAIL] = SPI_6358_RX_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [SPI_MSG_CTL] = SPI_6358_MSG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [SPI_MSG_DATA] = SPI_6358_MSG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [SPI_RX_DATA] = SPI_6358_RX_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct platform_device_id bcm63xx_spi_dev_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "bcm6348-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .name = "bcm6358-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct of_device_id bcm63xx_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int bcm63xx_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const unsigned long *bcm63xx_spireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int irq, bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct bcm63xx_spi *bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 num_cs = BCM63XX_SPI_MAX_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) bcm63xx_spireg = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) of_property_read_u32(dev->of_node, "num-cs", &num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (num_cs > BCM63XX_SPI_MAX_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) num_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) num_cs = BCM63XX_SPI_MAX_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else if (pdev->id_entry->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const struct platform_device_id *match = pdev->id_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bcm63xx_spireg = (const unsigned long *)match->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bus_num = BCM63XX_SPI_BUS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk = devm_clk_get(dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(dev, "no clock for device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) reset = devm_reset_control_get_optional_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (IS_ERR(reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return PTR_ERR(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) master = spi_alloc_master(dev, sizeof(*bs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(dev, "out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) init_completion(&bs->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bs->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) bs->regs = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (IS_ERR(bs->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = PTR_ERR(bs->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bs->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bs->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bs->reg_offsets = bcm63xx_spireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pdev->name, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(dev, "unable to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) master->bus_num = bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) master->transfer_one_message = bcm63xx_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) master->mode_bits = MODEBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) master->max_transfer_size = bcm63xx_spi_max_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) master->max_message_size = bcm63xx_spi_max_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) master->auto_runtime_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Initialize hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = clk_prepare_enable(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = reset_control_reset(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(dev, "unable to reset device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* register and we are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(dev, "spi register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) r, irq, bs->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int bcm63xx_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct bcm63xx_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* reset spi block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bcm_spi_writeb(bs, 0, SPI_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* HW shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) clk_disable_unprepare(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int bcm63xx_spi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct bcm63xx_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spi_master_suspend(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_disable_unprepare(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int bcm63xx_spi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct spi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct bcm63xx_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = clk_prepare_enable(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spi_master_resume(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct platform_driver bcm63xx_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .name = "bcm63xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .pm = &bcm63xx_spi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .of_match_table = bcm63xx_spi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .id_table = bcm63xx_spi_dev_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .probe = bcm63xx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .remove = bcm63xx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) module_platform_driver(bcm63xx_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_ALIAS("platform:bcm63xx_spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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