Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Broadcom BCM2835 auxiliary SPI Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * the driver does not rely on the native chipselects at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * but only uses the gpio type chipselects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on: spi-bcm2835.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2015 Martin Sperl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* define polling limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static unsigned int polling_limit_us = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_param(polling_limit_us, uint, 0664);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_PARM_DESC(polling_limit_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		 "time in us to run a transfer in polling mode - if zero no polling is used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * spi register defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * note there is garbage in the "official" documentation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * so some data is taken from the file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * inside of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* SPI register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BCM2835_AUX_SPI_CNTL0	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BCM2835_AUX_SPI_CNTL1	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BCM2835_AUX_SPI_STAT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BCM2835_AUX_SPI_PEEK	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BCM2835_AUX_SPI_IO	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BCM2835_AUX_SPI_TXHOLD	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Bitfields in CNTL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BCM2835_AUX_SPI_CNTL0_SPEED	0xFFF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX	0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BCM2835_AUX_SPI_CNTL0_CS	0x000E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BCM2835_AUX_SPI_CNTL0_POSTINPUT	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BCM2835_AUX_SPI_CNTL0_VAR_CS	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD	0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define BCM2835_AUX_SPI_CNTL0_ENABLE	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define BCM2835_AUX_SPI_CNTL0_IN_RISING	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define BCM2835_AUX_SPI_CNTL0_OUT_RISING	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BCM2835_AUX_SPI_CNTL0_CPOL	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Bitfields in CNTL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Bitfields in STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define BCM2835_AUX_SPI_STAT_TX_LVL	0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define BCM2835_AUX_SPI_STAT_RX_LVL	0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define BCM2835_AUX_SPI_STAT_TX_FULL	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define BCM2835_AUX_SPI_STAT_TX_EMPTY	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define BCM2835_AUX_SPI_STAT_RX_FULL	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define BCM2835_AUX_SPI_STAT_RX_EMPTY	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define BCM2835_AUX_SPI_STAT_BUSY	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define BCM2835_AUX_SPI_STAT_BITCOUNT	0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct bcm2835aux_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 cntl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u64 count_transfer_polling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u64 count_transfer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u64 count_transfer_irq_after_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				      const char *dname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	char name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct dentry *dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* get full name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* the base directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	dir = debugfs_create_dir(name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	bs->debugfs_dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	debugfs_create_u64("count_transfer_polling", 0444, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			   &bs->count_transfer_polling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	debugfs_create_u64("count_transfer_irq", 0444, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			   &bs->count_transfer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			   &bs->count_transfer_irq_after_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	debugfs_remove_recursive(bs->debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	bs->debugfs_dir = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				      const char *dname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return readl(bs->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				 u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	writel(val, bs->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int count = min(bs->rx_len, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (bs->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		switch (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			*bs->rx_buf++ = (data >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			*bs->rx_buf++ = (data >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			*bs->rx_buf++ = (data >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			/* fallthrough - no default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bs->rx_len -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	bs->pending -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* gather up to 3 bytes to write to the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	count = min(bs->tx_len, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		data |= byte << (8 * (2 - i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* and set the variable bit-length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	data |= (count * 8) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* and decrement length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bs->tx_len -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	bs->pending += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* write to the correct TX-register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (bs->tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* disable spi clearing fifo and interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* check if we have data to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	     stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		bcm2835aux_rd_fifo(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* check if we have data to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	while (bs->tx_len &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	       (bs->pending < 12) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		bcm2835aux_wr_fifo(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* IRQ may be shared, so return if our interrupts are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	      (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* do common fifo handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	bcm2835aux_spi_transfer_helper(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (!bs->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		/* disable tx fifo empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			BCM2835_AUX_SPI_CNTL1_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* and if rx_len is 0 then disable interrupts and wake up completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!bs->rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		complete(&master->xfer_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 					     struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 					     struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		BCM2835_AUX_SPI_CNTL1_TXEMPTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		BCM2835_AUX_SPI_CNTL1_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* and wait for finish... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					   struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					   struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	bs->count_transfer_irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* fill in registers and fifos before enabling interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* fill in tx fifo with data before enabling interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	while ((bs->tx_len) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	       (bs->pending < 12) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		bcm2835aux_wr_fifo(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* now run the interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 					    struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 					struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	bs->count_transfer_polling++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* configure spi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* set the timeout to at least 2 jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* loop until finished the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	while (bs->rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		/* do common fifo handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		bcm2835aux_spi_transfer_helper(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		/* there is still data pending to read check the timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (bs->rx_len && time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			dev_dbg_ratelimited(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 					    "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 					    jiffies - timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					    bs->tx_len, bs->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			/* forward to interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			bs->count_transfer_irq_after_poll++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return __bcm2835aux_spi_transfer_one_irq(master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 							       spi, tfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* and return without waiting for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int bcm2835aux_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				       struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				       struct spi_transfer *tfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	unsigned long spi_hz, clk_hz, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	unsigned long hz_per_byte, byte_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* calculate the registers to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 * note that we use the variable data mode, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 * is not optimal for longer transfers as we waste registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	 * resulting (potentially) in more interrupts when transferring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	 * more than 12 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* set clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	spi_hz = tfr->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	clk_hz = clk_get_rate(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (spi_hz >= clk_hz / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	} else if (spi_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	} else { /* the slowest we can go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* mask out old speed from previous spi_transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	/* set the new speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* set transmit buffers and length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	bs->tx_buf = tfr->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	bs->rx_buf = tfr->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	bs->tx_len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	bs->rx_len = tfr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	bs->pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* Calculate the estimated time in us the transfer runs.  Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	 * there are are 2 idle clocks cycles after each chunk getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	 * transferred - in our case the chunk size is 3 bytes, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	 * approximate this by 9 cycles/byte.  This is used to find the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * 30 µs per 300,000 Hz of bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* run in polling mode for short transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (tfr->len < byte_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	/* run in interrupt mode for all others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int bcm2835aux_spi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 					  struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	/* handle all the modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (spi->mode & SPI_CPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 					    struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	bcm2835aux_spi_reset_hw(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void bcm2835aux_spi_handle_err(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 				      struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	bcm2835aux_spi_reset_hw(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int bcm2835aux_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	/* sanity check for native cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (spi->mode & SPI_NO_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (gpio_is_valid(spi->cs_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		/* with gpio-cs set the GPIO to the correct level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		 * and as output (in case the dt has the gpio not configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		 * as output but native cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		ret = gpio_direction_output(spi->cs_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 					    (spi->mode & SPI_CS_HIGH) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 				"could not set gpio %i as output: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				spi->cs_gpio, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	/* for dt-backwards compatibility: only support native on CS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	 * known things not supported with broken native CS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	 * * multiple chip-selects: cs0-cs2 are all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	 *     simultaniously asserted whenever there is a transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	 *     this even includes SPI_NO_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	 * * SPI_CS_HIGH: cs are always asserted low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	 * * cs_change: cs is deasserted after each spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	 * * cs_delay_usec: cs is always deasserted one SCK cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	 *     after the last transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	 * probably more...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	dev_warn(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		 "Native CS is not supported - please configure cs-gpio in device-tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (spi->chip_select == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int bcm2835aux_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	struct bcm2835aux_spi *bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	unsigned long clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	/* even though the driver never officially supported native CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	 * allow a single native CS for legacy DT support purposes when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	 * no cs-gpio is configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	 * Known limitations for native cs are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	 *     whenever there is a transfer -  this even includes SPI_NO_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	 * * SPI_CS_HIGH: is ignores - cs are always asserted low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	 * * cs_change: cs is deasserted after each spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	 * * cs_delay_usec: cs is always deasserted one SCK cycle after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	 *     a spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	master->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	master->setup = bcm2835aux_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	master->transfer_one = bcm2835aux_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	master->handle_err = bcm2835aux_spi_handle_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	master->prepare_message = bcm2835aux_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	master->unprepare_message = bcm2835aux_spi_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	/* the main area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	bs->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	if (IS_ERR(bs->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		return PTR_ERR(bs->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	bs->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	if (IS_ERR(bs->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		err = PTR_ERR(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		dev_err(&pdev->dev, "could not get clk: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	bs->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	if (bs->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		return bs->irq ? bs->irq : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	/* this also enables the HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	err = clk_prepare_enable(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	/* just checking if the clock returns a sane value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	clk_hz = clk_get_rate(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	if (!clk_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		dev_err(&pdev->dev, "clock returns 0 Hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	/* reset SPI-HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	bcm2835aux_spi_reset_hw(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	err = devm_request_irq(&pdev->dev, bs->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 			       bcm2835aux_spi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 			       IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 			       dev_name(&pdev->dev), master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	err = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	clk_disable_unprepare(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int bcm2835aux_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	bcm2835aux_debugfs_remove(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	bcm2835aux_spi_reset_hw(bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	/* disable the HW block by releasing the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	clk_disable_unprepare(bs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct of_device_id bcm2835aux_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	{ .compatible = "brcm,bcm2835-aux-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct platform_driver bcm2835aux_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		.name		= "spi-bcm2835aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		.of_match_table	= bcm2835aux_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.probe		= bcm2835aux_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.remove		= bcm2835aux_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) module_platform_driver(bcm2835aux_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_LICENSE("GPL");