^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __SPI_BCM_QSPI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __SPI_BCM_QSPI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* BSPI interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define INTR_BSPI_LR_OVERREAD_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define INTR_BSPI_LR_SESSION_DONE_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define INTR_BSPI_LR_IMPATIENT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INTR_BSPI_LR_SESSION_ABORTED_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INTR_BSPI_LR_FULLNESS_REACHED_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BSPI_LR_INTERRUPTS_DATA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) (INTR_BSPI_LR_SESSION_DONE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) INTR_BSPI_LR_FULLNESS_REACHED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BSPI_LR_INTERRUPTS_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) (INTR_BSPI_LR_OVERREAD_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) INTR_BSPI_LR_IMPATIENT_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) INTR_BSPI_LR_SESSION_ABORTED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BSPI_LR_INTERRUPTS_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) (BSPI_LR_INTERRUPTS_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) BSPI_LR_INTERRUPTS_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* MSPI Interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INTR_MSPI_HALTED_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INTR_MSPI_DONE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSPI_INTERRUPTS_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (INTR_MSPI_DONE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) INTR_MSPI_HALTED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QSPI_INTERRUPTS_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (MSPI_INTERRUPTS_ALL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BSPI_LR_INTERRUPTS_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct dev_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MSPI_DONE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) BSPI_DONE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) BSPI_ERR = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MSPI_BSPI_DONE = 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct bcm_qspi_soc_intc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *soc_intc, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *soc_intc, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *soc_intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Read controller register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Write controller register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline void bcm_qspi_writel(bool be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int data, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) iowrite32be(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u32 get_qspi_mask(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case MSPI_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return INTR_MSPI_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case BSPI_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return BSPI_LR_INTERRUPTS_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case MSPI_BSPI_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return QSPI_INTERRUPTS_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case BSPI_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return BSPI_LR_INTERRUPTS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* The common driver functions to be called by the SoC platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int bcm_qspi_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct bcm_qspi_soc_intc *soc_intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int bcm_qspi_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* pm_ops used by the SoC platform driver called on PM suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) extern const struct dev_pm_ops bcm_qspi_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif /* __SPI_BCM_QSPI_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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