^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "spi-bcm-qspi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_NAME "bcm_qspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* BSPI register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BSPI_REVISION_ID 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BSPI_SCRATCH 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BSPI_MAST_N_BOOT_CTRL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BSPI_BUSY_STATUS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BSPI_INTR_STATUS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BSPI_B0_STATUS 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BSPI_B0_CTRL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BSPI_B1_STATUS 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BSPI_B1_CTRL 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BSPI_STRAP_OVERRIDE_CTRL 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BSPI_FLEX_MODE_ENABLE 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BSPI_BITS_PER_CYCLE 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BSPI_BITS_PER_PHASE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BSPI_CMD_AND_MODE_BYTE 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BSPI_BSPI_XOR_VALUE 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BSPI_BSPI_XOR_ENABLE 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BSPI_BSPI_PIO_MODE_ENABLE 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BSPI_BSPI_PIO_IODIR 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BSPI_BSPI_PIO_DATA 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* RAF register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BSPI_RAF_START_ADDR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BSPI_RAF_NUM_WORDS 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BSPI_RAF_CTRL 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BSPI_RAF_FULLNESS 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BSPI_RAF_WATERMARK 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BSPI_RAF_STATUS 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BSPI_RAF_READ_DATA 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BSPI_RAF_WORD_CNT 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BSPI_RAF_CURR_ADDR 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Override mode masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BSPI_ADDRLEN_3BYTES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BSPI_ADDRLEN_4BYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BSPI_RAF_CTRL_START_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BSPI_BPP_MODE_SELECT_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BSPI_READ_LENGTH 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* MSPI register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MSPI_SPCR0_LSB 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MSPI_SPCR0_MSB 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MSPI_SPCR1_LSB 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MSPI_SPCR1_MSB 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MSPI_NEWQP 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MSPI_ENDQP 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MSPI_SPCR2 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSPI_MSPI_STATUS 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSPI_CPTQP 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSPI_SPCR3 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSPI_REV 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSPI_TXRAM 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSPI_RXRAM 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSPI_CDRAM 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSPI_WRITE_LOCK 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MSPI_MASTER_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSPI_NUM_CDRAM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSPI_CDRAM_CONT_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSPI_CDRAM_BITSE_BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSPI_CDRAM_PCS 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSPI_SPCR2_SPE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSPI_SPCR3_FASTBR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSPI_SPCR3_FASTDT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~(BIT(10) | BIT(11)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSPI_MSPI_STATUS_SPIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INTR_BASE_BIT_SHIFT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INTR_COUNT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NUM_CHIPSELECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QSPI_SPBR_MAX 255U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSPI_BASE_FREQ 27000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OPCODE_DIOR 0xBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OPCODE_QIOR 0xEB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OPCODE_DIOR_4B 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OPCODE_QIOR_4B 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAX_CMD_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ADDR_4MB_MASK GENMASK(22, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* stop at end of transfer, no other reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TRANS_STATUS_BREAK_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* stop at end of spi_message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TRANS_STATUS_BREAK_EOM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* stop at end of spi_transfer if delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TRANS_STATUS_BREAK_DELAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* stop at end of spi_transfer if cs_change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TRANS_STATUS_BREAK_CS_CHANGE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* stop if we run out of bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TRANS_STATUS_BREAK_NO_BYTES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* events that make us stop filling TX slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TRANS_STATUS_BREAK_DELAY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TRANS_STATUS_BREAK_CS_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* events that make us deassert CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TRANS_STATUS_BREAK_CS_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct bcm_qspi_parms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct bcm_xfer_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool flex_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum base_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CHIP_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BASEMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum irq_source {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SINGLE_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MUXED_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct bcm_qspi_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const irq_handler_t irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int irq_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct bcm_qspi_dev_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const struct bcm_qspi_irq *irqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct qspi_trans {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct spi_transfer *trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool mspi_last_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct bcm_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 base_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __iomem *base[BASEMAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Some SoCs provide custom interrupt status register(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct bcm_qspi_soc_intc *soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct bcm_qspi_parms last_parms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct qspi_trans trans_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int curr_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int bspi_maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int bspi_min_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int bspi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct spi_mem_op *bspi_rf_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 bspi_rf_op_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 bspi_rf_op_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 bspi_rf_op_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct bcm_xfer_mode xfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 s3_strap_override_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) bool bspi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bool big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct bcm_qspi_dev_id *dev_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct completion mspi_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct completion bspi_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 mspi_maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 mspi_min_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bool mspi_spcr3_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline bool has_bspi(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return qspi->bspi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* hardware supports spcr3 and fast baud-rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!has_bspi(qspi) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ((qspi->mspi_maj_rev >= 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (qspi->mspi_min_rev >= 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* hardware supports sys clk 108Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ((qspi->mspi_maj_rev >= 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (qspi->mspi_min_rev >= 6))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (bcm_qspi_has_fastbr(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Read qspi controller register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Write qspi controller register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int offset, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* BSPI helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* this should normally finish within 10us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (qspi->bspi_maj_rev < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bcm_qspi_bspi_busy_poll(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Force rising edge for the b0/b1 'flush' field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* BSPI v3 LR is LE only, convert data to host endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (bcm_qspi_bspi_ver_three(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) data = le32_to_cpu(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bcm_qspi_bspi_busy_poll(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BSPI_RAF_CTRL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) BSPI_RAF_CTRL_CLEAR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bcm_qspi_bspi_flush_prefetch_buffers(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) data = bcm_qspi_bspi_lr_read_fifo(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (likely(qspi->bspi_rf_op_len >= 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) IS_ALIGNED((uintptr_t)buf, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) buf[qspi->bspi_rf_op_idx++] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) qspi->bspi_rf_op_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Read out remaining bytes, make sure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) while (qspi->bspi_rf_op_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *cbuf++ = (u8)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) qspi->bspi_rf_op_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int bpp, int bpc, int flex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct spi_mem_op *op, int hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int bpc = 0, bpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 command = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int addrlen = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int flex_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) width, addrlen, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (addrlen == BSPI_ADDRLEN_4BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bpp = BSPI_BPP_ADDR_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case SPI_NBITS_SINGLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (addrlen == BSPI_ADDRLEN_3BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* default mode, does not need flex_cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) flex_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bpc = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (hp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bpc |= 0x00010100; /* address and mode are 2-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bpp = BSPI_BPP_MODE_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bpc = 0x00000002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (hp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) bpc |= 0x00020200; /* address and mode are 4-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bpp |= BSPI_BPP_MODE_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct spi_mem_op *op, int hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int addrlen = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) width, addrlen, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case SPI_NBITS_SINGLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* clear quad/dual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* clear dual mode and set quad mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* clear quad mode set dual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (addrlen == BSPI_ADDRLEN_4BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* set 4byte mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* clear 4 byte mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* set the override mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) const struct spi_mem_op *op, int hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int addrlen = op->addr.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* default mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) qspi->xfer_mode.flex_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!bcm_qspi_bspi_ver_three(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (val & mask || qspi->s3_strap_override_ctrl & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) qspi->xfer_mode.flex_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) error = bcm_qspi_bspi_set_override(qspi, op, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (qspi->xfer_mode.flex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_warn(&qspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) width, addrlen, hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else if (qspi->xfer_mode.width != width ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) qspi->xfer_mode.addrlen != addrlen ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) qspi->xfer_mode.hp != hp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) qspi->xfer_mode.width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) qspi->xfer_mode.addrlen = addrlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) qspi->xfer_mode.hp = hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_dbg(&qspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "cs:%d %d-lane output, %d-byte address%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) qspi->curr_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) qspi->xfer_mode.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) qspi->xfer_mode.addrlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) qspi->bspi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bcm_qspi_bspi_flush_prefetch_buffers(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) qspi->bspi_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bcm_qspi_bspi_busy_poll(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 rd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (cs >= 0 && qspi->base[CHIP_SELECT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) wr = (rd & ~0xff) | (1 << cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (rd == wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) qspi->curr_cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* MSPI helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct bcm_qspi_parms *xp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 spcr, spbr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (xp->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) spbr = qspi->base_clk / (2 * xp->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!qspi->mspi_maj_rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* legacy controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spcr = MSPI_MASTER_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) spcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* for 16 bit the data should be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (xp->bits_per_word != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) spcr |= xp->bits_per_word << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) spcr |= xp->mode & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (bcm_qspi_has_fastbr(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* enable fastbr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) spcr |= MSPI_SPCR3_FASTBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (bcm_qspi_has_sysclk_108(qspi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* SYSCLK_108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) spcr |= MSPI_SPCR3_SYSCLKSEL_108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) qspi->base_clk = MSPI_BASE_FREQ * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Change spbr as we changed sysclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) qspi->last_parms = *xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct spi_transfer *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct bcm_qspi_parms xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) xp.speed_hz = trans->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) xp.bits_per_word = trans->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) xp.mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) bcm_qspi_hw_set_parms(qspi, &xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int bcm_qspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct bcm_qspi_parms *xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (spi->bits_per_word > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) xp = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!xp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) xp = kzalloc(sizeof(*xp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!xp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) spi_set_ctldata(spi, xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) xp->speed_hz = spi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) xp->mode = spi->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (spi->bits_per_word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) xp->bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) xp->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct qspi_trans *qt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (qt->mspi_last_trans &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spi_transfer_is_last(qspi->master, qt->trans))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct qspi_trans *qt, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int ret = TRANS_STATUS_BREAK_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* count the last transferred bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (qt->trans->bits_per_word <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) qt->byte++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) qt->byte += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (qt->byte >= qt->trans->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* we're at the end of the spi_transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* in TX mode, need to pause for a delay or CS change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (qt->trans->delay_usecs &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (flags & TRANS_STATUS_BREAK_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret |= TRANS_STATUS_BREAK_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (qt->trans->cs_change &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (flags & TRANS_STATUS_BREAK_CS_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret |= TRANS_STATUS_BREAK_CS_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret |= TRANS_STATUS_BREAK_EOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret |= TRANS_STATUS_BREAK_NO_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) qt->trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* mask out reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 reg_offset = MSPI_RXRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 msb_offset = reg_offset + (slot << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void read_from_hw(struct bcm_qspi *qspi, int slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct qspi_trans tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bcm_qspi_disable_bspi(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (slots > MSPI_NUM_CDRAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tp = qspi->trans_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) for (slot = 0; slot < slots; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (tp.trans->bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 *buf = tp.trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(&qspi->pdev->dev, "RD %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) buf ? buf[tp.byte] : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u16 *buf = tp.trans->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_dbg(&qspi->pdev->dev, "RD %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf ? buf[tp.byte / 2] : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) update_qspi_trans_byte_count(qspi, &tp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) TRANS_STATUS_BREAK_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) qspi->trans_pos = tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 reg_offset = MSPI_TXRAM + (slot << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* mask out reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) bcm_qspi_write(qspi, MSPI, reg_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 reg_offset = MSPI_TXRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 msb_offset = reg_offset + (slot << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Return number of slots written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct qspi_trans tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int slot = 0, tstatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 mspi_cdram = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) bcm_qspi_disable_bspi(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tp = qspi->trans_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) bcm_qspi_update_parms(qspi, spi, tp.trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Run until end of transfer or reached the max data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) while (!tstatus && slot < MSPI_NUM_CDRAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (tp.trans->bits_per_word <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) const u8 *buf = tp.trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u8 val = buf ? buf[tp.byte] : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) write_txram_slot_u8(qspi, slot, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) const u16 *buf = tp.trans->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u16 val = buf ? buf[tp.byte / 2] : 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) write_txram_slot_u16(qspi, slot, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mspi_cdram = MSPI_CDRAM_CONT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mspi_cdram &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mspi_cdram |= (~(1 << spi->chip_select) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MSPI_CDRAM_PCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) MSPI_CDRAM_BITSE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) write_cdram_slot(qspi, slot, mspi_cdram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) tstatus = update_qspi_trans_byte_count(qspi, &tp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) TRANS_STATUS_BREAK_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) slot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * case 1) EOM =1, cs_change =0: SSb inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * case 2) EOM =1, cs_change =1: SSb stay active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * case 3) EOM =0, cs_change =0: SSb stay active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * case 4) EOM =0, cs_change =1: SSb inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) == TRANS_STATUS_BREAK_CS_CHANGE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ((tstatus & TRANS_STATUS_BREAK_DESELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) == TRANS_STATUS_BREAK_EOM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mspi_cdram = read_cdram_slot(qspi, slot - 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ~MSPI_CDRAM_CONT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) write_cdram_slot(qspi, slot - 1, mspi_cdram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Must flush previous writes before starting MSPI operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Set cont | spe | spifie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 addr = 0, len, rdlen, len_words, from = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned long timeo = msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (bcm_qspi_bspi_ver_three(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) from = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) bcm_qspi_chip_select(qspi, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * when using flex mode we need to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * the upper address byte to bspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (bcm_qspi_bspi_ver_three(qspi) == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) addr = from & 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) bcm_qspi_write(qspi, BSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!qspi->xfer_mode.flex_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) addr = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) addr = from & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (bcm_qspi_bspi_ver_three(qspi) == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) addr = (addr + 0xc00000) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * read into the entire buffer by breaking the reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * into RAF buffer read lengths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) qspi->bspi_rf_op_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (len > BSPI_READ_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) rdlen = BSPI_READ_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rdlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) reinit_completion(&qspi->bspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bcm_qspi_enable_bspi(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) len_words = (rdlen + 3) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) qspi->bspi_rf_op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) qspi->bspi_rf_op_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) qspi->bspi_rf_op_len = rdlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_dbg(&qspi->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (qspi->soc_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * clear soc MSPI and BSPI interrupts and enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * BSPI interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Must flush previous writes before starting BSPI operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) bcm_qspi_bspi_lr_start(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* set msg return length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) addr += rdlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) len -= rdlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } while (len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int bcm_qspi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct spi_transfer *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct bcm_qspi *qspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned long timeo = msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!spi->cs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) bcm_qspi_chip_select(qspi, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) qspi->trans_pos.trans = trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) qspi->trans_pos.byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) while (qspi->trans_pos.byte < trans->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) reinit_completion(&qspi->mspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) slots = write_to_hw(qspi, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) read_from_hw(qspi, slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) bcm_qspi_enable_bspi(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct spi_master *master = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct bcm_qspi *qspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct spi_transfer t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u8 cmd[6] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) memset(cmd, 0, sizeof(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* opcode is in cmd[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) cmd[0] = op->cmd.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) for (i = 0; i < op->addr.nbytes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) t[0].tx_buf = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) t[0].bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) t[0].tx_nbits = op->cmd.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* lets mspi know that this is not last transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) qspi->trans_pos.mspi_last_trans = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = bcm_qspi_transfer_one(master, spi, &t[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) qspi->trans_pos.mspi_last_trans = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) t[1].rx_buf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) t[1].len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) t[1].rx_nbits = op->data.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) t[1].bits_per_word = spi->bits_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = bcm_qspi_transfer_one(master, spi, &t[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct spi_device *spi = mem->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bool mspi_read = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) u32 addr = 0, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u_char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) op->data.dir != SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) buf = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) addr = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) len = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (bcm_qspi_bspi_ver_three(qspi) == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * The address coming into this function is a raw flash offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * But for BSPI <= V3, we need to convert it to a remapped BSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * address. If it crosses a 4MB boundary, just revert back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * using MSPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) addr = (addr + 0xc00000) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if ((~ADDR_4MB_MASK & addr) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) (~ADDR_4MB_MASK & (addr + len - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mspi_read = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* non-aligned and very short transfers are handled by MSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) len < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mspi_read = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (mspi_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return bcm_qspi_mspi_exec_mem_op(spi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = bcm_qspi_bspi_exec_mem_op(spi, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void bcm_qspi_cleanup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) kfree(xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct bcm_qspi *qspi = qspi_dev_id->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (status & MSPI_MSPI_STATUS_SPIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) status &= ~MSPI_MSPI_STATUS_SPIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (qspi->soc_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) complete(&qspi->mspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct bcm_qspi *qspi = qspi_dev_id->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u32 status = qspi_dev_id->irqp->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (qspi->bspi_enabled && qspi->bspi_rf_op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) bcm_qspi_bspi_lr_data_read(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (qspi->bspi_rf_op_len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) qspi->bspi_rf_op = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (qspi->soc_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* disable soc BSPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* indicate done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) status = INTR_BSPI_LR_SESSION_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (qspi->bspi_rf_op_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) bcm_qspi_bspi_lr_clear(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) bcm_qspi_bspi_flush_prefetch_buffers(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (qspi->soc_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* clear soc BSPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) status &= INTR_BSPI_LR_SESSION_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) complete(&qspi->bspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct bcm_qspi *qspi = qspi_dev_id->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_err(&qspi->pdev->dev, "BSPI INT error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) qspi->bspi_rf_op_status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (qspi->soc_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* clear soc interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) complete(&qspi->bspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct bcm_qspi *qspi = qspi_dev_id->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (soc_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (status & MSPI_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) else if (status & BSPI_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) else if (status & BSPI_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct bcm_qspi_irq qspi_irq_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .irq_name = "spi_lr_fullness_reached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .irq_handler = bcm_qspi_bspi_lr_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .irq_name = "spi_lr_session_aborted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .irq_name = "spi_lr_impatient",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .mask = INTR_BSPI_LR_IMPATIENT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .irq_name = "spi_lr_session_done",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .irq_handler = bcm_qspi_bspi_lr_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #ifdef QSPI_INT_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* this interrupt is for debug purposes only, dont request irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .irq_name = "spi_lr_overread",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .mask = INTR_BSPI_LR_OVERREAD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .irq_name = "mspi_done",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .irq_handler = bcm_qspi_mspi_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .mask = INTR_MSPI_DONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .irq_name = "mspi_halted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .irq_handler = bcm_qspi_mspi_l2_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .mask = INTR_MSPI_HALTED_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* single muxed L1 interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .irq_name = "spi_l1_intr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .irq_handler = bcm_qspi_l1_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .irq_source = MUXED_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .mask = QSPI_INTERRUPTS_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) qspi->bspi_maj_rev = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) qspi->bspi_min_rev = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!(bcm_qspi_bspi_ver_three(qspi))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Force mapping of BSPI address -> flash offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) qspi->bspi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) bcm_qspi_disable_bspi(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct bcm_qspi_parms parms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) parms.mode = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) parms.bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) parms.speed_hz = qspi->max_speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bcm_qspi_hw_set_parms(qspi, &parms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) bcm_qspi_bspi_init(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (has_bspi(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .exec_op = bcm_qspi_exec_mem_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct bcm_qspi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) bool has_mspi_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) bool has_spcr3_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .has_mspi_rev = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .has_spcr3_sysclk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const struct bcm_qspi_data bcm_qspi_rev_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .has_mspi_rev = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .has_spcr3_sysclk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .has_mspi_rev = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .has_spcr3_sysclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static const struct of_device_id bcm_qspi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .compatible = "brcm,spi-bcm7445-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .data = &bcm_qspi_rev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .compatible = "brcm,spi-bcm-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .data = &bcm_qspi_no_rev_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .compatible = "brcm,spi-bcm7216-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .data = &bcm_qspi_spcr3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .compatible = "brcm,spi-bcm7278-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .data = &bcm_qspi_spcr3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) int bcm_qspi_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct bcm_qspi_soc_intc *soc_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) const struct of_device_id *of_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) const struct bcm_qspi_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct bcm_qspi *qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int irq, ret = 0, num_ints = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) u32 rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) const char *name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) int num_irqs = ARRAY_SIZE(qspi_irq_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* We only support device-tree instantiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev_err(dev, "error allocating spi_master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) qspi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (IS_ERR(qspi->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return PTR_ERR(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) qspi->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) qspi->trans_pos.trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) qspi->trans_pos.byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) qspi->trans_pos.mspi_last_trans = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) qspi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) master->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) master->setup = bcm_qspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) master->transfer_one = bcm_qspi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) master->mem_ops = &bcm_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) master->cleanup = bcm_qspi_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) master->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) master->num_chipselect = NUM_CHIPSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) master->use_gpio_descriptors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) qspi->big_endian = of_device_is_big_endian(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (!of_property_read_u32(dev->of_node, "num-cs", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) master->num_chipselect = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "mspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) qspi->base[MSPI] = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (IS_ERR(qspi->base[MSPI]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return PTR_ERR(qspi->base[MSPI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) qspi->base[BSPI] = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (IS_ERR(qspi->base[BSPI]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return PTR_ERR(qspi->base[BSPI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) qspi->bspi_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) qspi->bspi_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (IS_ERR(qspi->base[CHIP_SELECT]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return PTR_ERR(qspi->base[CHIP_SELECT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (!qspi->dev_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Some SoCs integrate spi controller (e.g., its interrupt bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * in specific ways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (soc_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) qspi->soc_intc = soc_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) qspi->soc_intc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (qspi->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = clk_prepare_enable(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev_err(dev, "failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) goto qspi_probe_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) qspi->base_clk = clk_get_rate(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) qspi->base_clk = MSPI_BASE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (data->has_mspi_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* some older revs do not have a MSPI_REV register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if ((rev & 0xff) == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) rev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) qspi->mspi_maj_rev = (rev >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) qspi->mspi_min_rev = rev & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * On SW resets it is possible to have the mask still enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * Need to disable the mask and clear the status while we init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) bcm_qspi_hw_uninit(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) for (val = 0; val < num_irqs; val++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) name = qspi_irq_tab[val].irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* get the l2 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) irq = platform_get_irq_byname_optional(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) } else if (!num_ints && soc_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* all mspi, bspi intrs muxed to one L1 intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) qspi_irq_tab[val].irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) &qspi->dev_ids[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev_err(&pdev->dev, "IRQ %s not found\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) goto qspi_unprepare_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) qspi->dev_ids[val].dev = qspi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) num_ints++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) qspi_irq_tab[val].irq_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!num_ints) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) goto qspi_unprepare_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) bcm_qspi_hw_init(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) init_completion(&qspi->mspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) init_completion(&qspi->bspi_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) qspi->curr_cs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) platform_set_drvdata(pdev, qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) qspi->xfer_mode.width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) qspi->xfer_mode.addrlen = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) qspi->xfer_mode.hp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(dev, "can't register master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) goto qspi_reg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) qspi_reg_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) bcm_qspi_hw_uninit(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) qspi_unprepare_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) qspi_probe_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) kfree(qspi->dev_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* probe function to be called by SoC specific platform driver probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) EXPORT_SYMBOL_GPL(bcm_qspi_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int bcm_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) struct bcm_qspi *qspi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) spi_unregister_master(qspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) bcm_qspi_hw_uninit(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) kfree(qspi->dev_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* function to be called by SoC specific platform driver remove() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) EXPORT_SYMBOL_GPL(bcm_qspi_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static int __maybe_unused bcm_qspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct bcm_qspi *qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* store the override strap value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (!bcm_qspi_bspi_ver_three(qspi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) qspi->s3_strap_override_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) spi_master_suspend(qspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) clk_disable_unprepare(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) bcm_qspi_hw_uninit(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static int __maybe_unused bcm_qspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct bcm_qspi *qspi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) bcm_qspi_hw_init(qspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) bcm_qspi_chip_select(qspi, qspi->curr_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (qspi->soc_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* enable MSPI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ret = clk_prepare_enable(qspi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) spi_master_resume(qspi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* pm_ops to be called by SoC specific platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) MODULE_AUTHOR("Kamal Dasu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MODULE_DESCRIPTION("Broadcom QSPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags