^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI-Engine SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPI_ENGINE_REG_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPI_ENGINE_REG_RESET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPI_ENGINE_REG_INT_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPI_ENGINE_REG_INT_PENDING 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPI_ENGINE_REG_INT_SOURCE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPI_ENGINE_REG_SYNC_ID 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPI_ENGINE_REG_CMD_FIFO 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPI_ENGINE_INT_SYNC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI_ENGINE_CONFIG_CPHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI_ENGINE_CONFIG_CPOL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPI_ENGINE_CONFIG_3WIRE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPI_ENGINE_INST_TRANSFER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPI_ENGINE_INST_ASSERT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPI_ENGINE_INST_WRITE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPI_ENGINE_INST_MISC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPI_ENGINE_CMD_REG_CONFIG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPI_ENGINE_MISC_SYNC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPI_ENGINE_MISC_SLEEP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPI_ENGINE_TRANSFER_WRITE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPI_ENGINE_TRANSFER_READ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPI_ENGINE_CMD(inst, arg1, arg2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (((inst) << 12) | ((arg1) << 8) | (arg2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_ENGINE_CMD_TRANSFER(flags, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPI_ENGINE_CMD_ASSERT(delay, cs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPI_ENGINE_CMD_WRITE(reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI_ENGINE_CMD_SLEEP(delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPI_ENGINE_CMD_SYNC(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct spi_engine_program {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uint16_t instructions[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spi_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct spi_message *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct spi_engine_program *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned cmd_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const uint16_t *cmd_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_transfer *tx_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int tx_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const uint8_t *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct spi_transfer *rx_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int rx_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint8_t *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int sync_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int completed_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void spi_engine_program_add_cmd(struct spi_engine_program *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool dry, uint16_t cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!dry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) p->instructions[p->length] = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) p->length++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned int spi_engine_get_config(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (spi->mode & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) config |= SPI_ENGINE_CONFIG_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (spi->mode & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) config |= SPI_ENGINE_CONFIG_CPHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (spi->mode & SPI_3WIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config |= SPI_ENGINE_CONFIG_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct spi_device *spi, struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) xfer->speed_hz * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (clk_div > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_div = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else if (clk_div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_div -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int len = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int n = min(len, 256U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) flags |= SPI_ENGINE_TRANSFER_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) flags |= SPI_ENGINE_TRANSFER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spi_engine_program_add_cmd(p, dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) len -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct spi_engine *spi_engine, unsigned int clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (xfer->delay_usecs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) delay = xfer->delay_usecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) delay = spi_delay_to_ns(&xfer->delay, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (delay < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) delay /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) while (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int n = min(t, 256U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) t -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct spi_device *spi, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mask ^= BIT(spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int spi_engine_compile_message(struct spi_engine *spi_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct spi_message *msg, bool dry, struct spi_engine_program *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int clk_div, new_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool cs_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk_div = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spi_engine_program_add_cmd(p, dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spi_engine_get_config(spi)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) list_for_each_entry(xfer, &msg->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (new_clk_div != clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_div = new_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spi_engine_program_add_cmd(p, dry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spi_engine_gen_cs(p, dry, spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spi_engine_gen_xfer(p, dry, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spi_engine_gen_sleep(p, dry, spi_engine, clk_div, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cs_change = xfer->cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (list_is_last(&xfer->transfer_list, &msg->transfers))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cs_change = !cs_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (cs_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spi_engine_gen_cs(p, dry, spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void spi_engine_xfer_next(struct spi_engine *spi_engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct spi_transfer **_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct spi_message *msg = spi_engine->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct spi_transfer *xfer = *_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) xfer = list_first_entry(&msg->transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct spi_transfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) xfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) xfer = list_next_entry(xfer, transfer_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *_xfer = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void spi_engine_tx_next(struct spi_engine *spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct spi_transfer *xfer = spi_engine->tx_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spi_engine_xfer_next(spi_engine, &xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } while (xfer && !xfer->tx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spi_engine->tx_xfer = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spi_engine->tx_length = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spi_engine->tx_buf = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spi_engine->tx_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void spi_engine_rx_next(struct spi_engine *spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct spi_transfer *xfer = spi_engine->rx_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spi_engine_xfer_next(spi_engine, &xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } while (xfer && !xfer->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spi_engine->rx_xfer = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spi_engine->rx_length = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spi_engine->rx_buf = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) spi_engine->rx_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int n, m, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const uint16_t *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) while (n && spi_engine->cmd_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) m = min(n, spi_engine->cmd_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) buf = spi_engine->cmd_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (i = 0; i < m; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel_relaxed(buf[i], addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spi_engine->cmd_buf += m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spi_engine->cmd_length -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) n -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return spi_engine->cmd_length != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int n, m, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const uint8_t *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (n && spi_engine->tx_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) m = min(n, spi_engine->tx_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) buf = spi_engine->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (i = 0; i < m; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) writel_relaxed(buf[i], addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spi_engine->tx_buf += m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spi_engine->tx_length -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) n -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (spi_engine->tx_length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spi_engine_tx_next(spi_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return spi_engine->tx_length != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int n, m, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint8_t *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) while (n && spi_engine->rx_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) m = min(n, spi_engine->rx_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) buf = spi_engine->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) for (i = 0; i < m; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) buf[i] = readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spi_engine->rx_buf += m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spi_engine->rx_length -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) n -= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (spi_engine->rx_length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spi_engine_rx_next(spi_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return spi_engine->rx_length != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static irqreturn_t spi_engine_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct spi_master *master = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct spi_engine *spi_engine = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int disable_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pending & SPI_ENGINE_INT_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel_relaxed(SPI_ENGINE_INT_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spi_engine->completed_id = readl_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_lock(&spi_engine->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!spi_engine_write_cmd_fifo(spi_engine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!spi_engine_write_tx_fifo(spi_engine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!spi_engine_read_rx_fifo(spi_engine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (pending & SPI_ENGINE_INT_SYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (spi_engine->msg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spi_engine->completed_id == spi_engine->sync_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct spi_message *msg = spi_engine->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) kfree(spi_engine->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msg->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msg->actual_length = msg->frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) spi_engine->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) disable_int |= SPI_ENGINE_INT_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (disable_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spi_engine->int_enable &= ~disable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel_relaxed(spi_engine->int_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_unlock(&spi_engine->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int spi_engine_transfer_one_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct spi_engine_program p_dry, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct spi_engine *spi_engine = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int int_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) p_dry.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spi_engine_compile_message(spi_engine, msg, true, &p_dry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) size = sizeof(*p->instructions) * (p_dry.length + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) p = kzalloc(sizeof(*p) + size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spi_engine_compile_message(spi_engine, msg, false, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_lock_irqsave(&spi_engine->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) spi_engine_program_add_cmd(p, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SPI_ENGINE_CMD_SYNC(spi_engine->sync_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spi_engine->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) spi_engine->p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spi_engine->cmd_buf = p->instructions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) spi_engine->cmd_length = p->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (spi_engine_write_cmd_fifo(spi_engine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spi_engine_tx_next(spi_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (spi_engine_write_tx_fifo(spi_engine))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spi_engine_rx_next(spi_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (spi_engine->rx_length != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int_enable |= SPI_ENGINE_INT_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) writel_relaxed(int_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spi_engine->int_enable = int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_unlock_irqrestore(&spi_engine->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int spi_engine_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct spi_engine *spi_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!spi_engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) master = spi_alloc_master(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spi_master_set_devdata(master, spi_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) spin_lock_init(&spi_engine->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (IS_ERR(spi_engine->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = PTR_ERR(spi_engine->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (IS_ERR(spi_engine->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = PTR_ERR(spi_engine->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = clk_prepare_enable(spi_engine->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto err_put_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = clk_prepare_enable(spi_engine->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (IS_ERR(spi_engine->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = PTR_ERR(spi_engine->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto err_ref_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (SPI_ENGINE_VERSION_MAJOR(version) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SPI_ENGINE_VERSION_MAJOR(version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SPI_ENGINE_VERSION_MINOR(version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SPI_ENGINE_VERSION_PATCH(version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto err_ref_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto err_ref_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) master->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) master->transfer_one_message = spi_engine_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) master->num_chipselect = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = spi_register_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) free_irq(irq, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) err_ref_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_disable_unprepare(spi_engine->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_disable_unprepare(spi_engine->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) err_put_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int spi_engine_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct spi_engine *spi_engine = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) spi_unregister_master(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) free_irq(irq, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk_disable_unprepare(spi_engine->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_disable_unprepare(spi_engine->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct of_device_id spi_engine_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { .compatible = "adi,axi-spi-engine-1.00.a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_DEVICE_TABLE(of, spi_engine_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct platform_driver spi_engine_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .probe = spi_engine_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .remove = spi_engine_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "spi-engine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .of_match_table = spi_engine_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) module_platform_driver(spi_engine_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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