^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Armada-3700 SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Marvell Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Wilson Ding <dingwei@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Romain Perier <romain.perier@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRIVER_NAME "armada_3700_spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define A3700_SPI_MAX_SPEED_HZ 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define A3700_SPI_MAX_PRESCALE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define A3700_SPI_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SPI Register Offest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define A3700_SPI_IF_CTRL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define A3700_SPI_IF_CFG_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define A3700_SPI_DATA_OUT_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define A3700_SPI_DATA_IN_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define A3700_SPI_IF_INST_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define A3700_SPI_IF_ADDR_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define A3700_SPI_IF_RMODE_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define A3700_SPI_IF_HDR_CNT_REG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define A3700_SPI_IF_DIN_CNT_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define A3700_SPI_IF_TIME_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define A3700_SPI_INT_STAT_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define A3700_SPI_INT_MASK_REG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* A3700_SPI_IF_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define A3700_SPI_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define A3700_SPI_WFIFO_OVERFLOW BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define A3700_SPI_RFIFO_OVERFLOW BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define A3700_SPI_WFIFO_FULL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define A3700_SPI_WFIFO_EMPTY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define A3700_SPI_RFIFO_FULL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define A3700_SPI_RFIFO_EMPTY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define A3700_SPI_WFIFO_RDY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define A3700_SPI_RFIFO_RDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define A3700_SPI_XFER_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define A3700_SPI_XFER_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* A3700_SPI_IF_CFG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define A3700_SPI_WFIFO_THRS BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define A3700_SPI_RFIFO_THRS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define A3700_SPI_AUTO_CS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define A3700_SPI_DMA_RD_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define A3700_SPI_FIFO_MODE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define A3700_SPI_SRST BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define A3700_SPI_XFER_START BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define A3700_SPI_XFER_STOP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define A3700_SPI_INST_PIN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define A3700_SPI_ADDR_PIN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define A3700_SPI_DATA_PIN1 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define A3700_SPI_DATA_PIN0 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define A3700_SPI_FIFO_FLUSH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define A3700_SPI_RW_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define A3700_SPI_CLK_POL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define A3700_SPI_CLK_PHA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define A3700_SPI_BYTE_LEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define A3700_SPI_CLK_PRESCALE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define A3700_SPI_CLK_EVEN_OFFS (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define A3700_SPI_WFIFO_THRS_BIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define A3700_SPI_RFIFO_THRS_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define A3700_SPI_FIFO_THRS_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define A3700_SPI_DATA_PIN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* A3700_SPI_IF_HDR_CNT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define A3700_SPI_DUMMY_CNT_BIT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define A3700_SPI_DUMMY_CNT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define A3700_SPI_RMODE_CNT_BIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define A3700_SPI_RMODE_CNT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define A3700_SPI_ADDR_CNT_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define A3700_SPI_ADDR_CNT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define A3700_SPI_INSTR_CNT_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define A3700_SPI_INSTR_CNT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* A3700_SPI_IF_TIME_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define A3700_SPI_CLK_CAPT_EDGE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct a3700_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool xmit_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 wait_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return readl(a3700_spi->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(data, a3700_spi->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val &= ~A3700_SPI_AUTO_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val |= (A3700_SPI_EN << cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val &= ~(A3700_SPI_EN << cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int pin_mode, bool receiving)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (pin_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case SPI_NBITS_SINGLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case SPI_NBITS_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= A3700_SPI_DATA_PIN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case SPI_NBITS_QUAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val |= A3700_SPI_DATA_PIN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* RX during address reception uses 4-pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (receiving)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val |= A3700_SPI_ADDR_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val |= A3700_SPI_FIFO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val &= ~A3700_SPI_FIFO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int mode_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (mode_bits & SPI_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val |= A3700_SPI_CLK_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val &= ~A3700_SPI_CLK_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (mode_bits & SPI_CPHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val |= A3700_SPI_CLK_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val &= ~A3700_SPI_CLK_PHA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* For prescaler values over 15, we can only set it by steps of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 30. We only use this range from 16 to 30.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (prescale > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (prescale <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val |= A3700_SPI_CLK_CAPT_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (len == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val |= A3700_SPI_BYTE_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val &= ~A3700_SPI_BYTE_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) a3700_spi->byte_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int timeout = A3700_SPI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val |= A3700_SPI_FIFO_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!(val & A3700_SPI_FIFO_FLUSH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void a3700_spi_init(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct spi_master *master = a3700_spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Reset SPI unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val |= A3700_SPI_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) udelay(A3700_SPI_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val &= ~A3700_SPI_SRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Disable AUTO_CS and deactivate all chip-selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) a3700_spi_auto_cs_unset(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 0; i < master->num_chipselect; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) a3700_spi_deactivate_cs(a3700_spi, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Enable FIFO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) a3700_spi_fifo_mode_set(a3700_spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Set SPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) a3700_spi_mode_set(a3700_spi, master->mode_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Reset counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Mask the interrupts and clear cause bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct spi_master *master = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct a3700_spi *a3700_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) a3700_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Get interrupt causes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!cause || !(a3700_spi->wait_mask & cause))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* mask and acknowledge the SPI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Wake up the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) complete(&a3700_spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static bool a3700_spi_wait_completion(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct a3700_spi *a3700_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long timeout_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) a3700_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* SPI interrupt is edge-triggered, which means an interrupt will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * be generated only when detecting a specific status bit changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * from '0' to '1'. So when we start waiting for a interrupt, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * need to check status bit in control reg first, if it is already 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * then we do not need to wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (a3700_spi->wait_mask & ctrl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reinit_completion(&a3700_spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) a3700_spi->wait_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) timeout = wait_for_completion_timeout(&a3700_spi->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) timeout_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) a3700_spi->wait_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* there might be the case that right after we checked the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * status bits in this routine and before start to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * interrupt by wait_for_completion_timeout, the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * happens, to avoid missing it we need to double check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * status bits in control reg, if it is already 1, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * consider that we have the interrupt successfully and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * return true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (a3700_spi->wait_mask & ctrl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Timeout was reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static bool a3700_spi_transfer_wait(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int bit_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct a3700_spi *a3700_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) a3700_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) a3700_spi->wait_mask = bit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return a3700_spi_wait_completion(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void a3700_spi_transfer_setup(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct a3700_spi *a3700_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) a3700_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Use 4 bytes long transfers. Each transfer method has its way to deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * with the remaining bytes for non 4-bytes aligned transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) a3700_spi_bytelen_set(a3700_spi, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Initialize the working buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) a3700_spi->tx_buf = xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) a3700_spi->rx_buf = xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) a3700_spi->buf_len = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) a3700_spi_activate_cs(a3700_spi, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Clear the header registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Set header counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (a3700_spi->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * when tx data is not 4 bytes aligned, there will be unexpected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * bytes out of SPI output register, since it always shifts out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * as whole 4 bytes. This might cause incorrect transaction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * some devices. To avoid that, use SPI header count feature to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * transfer up to 3 bytes of data first, and then make the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * of data 4-byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) addr_cnt = a3700_spi->buf_len % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (addr_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) << A3700_SPI_ADDR_CNT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Update the buffer length to be transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) a3700_spi->buf_len -= addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* transfer 1~3 bytes through address count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) while (addr_cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val = (val << 8) | a3700_spi->tx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) a3700_spi->tx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return (val & A3700_SPI_WFIFO_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val = *(u32 *)a3700_spi->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) a3700_spi->buf_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) a3700_spi->tx_buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return (val & A3700_SPI_RFIFO_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (a3700_spi->buf_len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) memcpy(a3700_spi->rx_buf, &val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) a3700_spi->buf_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) a3700_spi->rx_buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * When remain bytes is not larger than 4, we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * avoid memory overwriting and just write the left rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * buffer bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) while (a3700_spi->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *a3700_spi->rx_buf = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) a3700_spi->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) a3700_spi->rx_buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int timeout = A3700_SPI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val |= A3700_SPI_XFER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!(val & A3700_SPI_XFER_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) a3700_spi_fifo_flush(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val &= ~A3700_SPI_XFER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int a3700_spi_prepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct spi_device *spi = message->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = clk_enable(a3700_spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Flush the FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = a3700_spi_fifo_flush(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) a3700_spi_mode_set(a3700_spi, spi->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int a3700_spi_transfer_one_fifo(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int ret = 0, timeout = A3700_SPI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned int nbits = 0, byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Make sure we use FIFO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) a3700_spi_fifo_mode_set(a3700_spi, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Configure FIFO thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) byte_len = xfer->bits_per_word >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) a3700_spi_fifo_thres_set(a3700_spi, byte_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) nbits = xfer->tx_nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) nbits = xfer->rx_nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Flush the FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) a3700_spi_fifo_flush(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Transfer first bytes of data when buffer is not 4-byte aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) a3700_spi_header_set(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (xfer->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Clear WFIFO, since it's last 2 bytes are shifted out during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * a read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Set read data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) a3700_spi->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Start READ transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val &= ~A3700_SPI_RW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val |= A3700_SPI_XFER_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else if (xfer->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Start Write transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * If there are data to be written to the SPI device, xmit_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * flag is set true; otherwise the instruction in SPI_INSTR does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * not require data to be written to the SPI device, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * xmit_data flag is set false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) while (a3700_spi->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (a3700_spi->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Wait wfifo ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!a3700_spi_transfer_wait(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) A3700_SPI_WFIFO_RDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "wait wfifo ready timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Fill up the wfifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = a3700_spi_fifo_write(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else if (a3700_spi->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Wait rfifo ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!a3700_spi_transfer_wait(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) A3700_SPI_RFIFO_RDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "wait rfifo ready timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Drain out the rfifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = a3700_spi_fifo_read(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Stop a write transfer in fifo mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * - wait all the bytes in wfifo to be shifted out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * - set XFER_STOP bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * - wait XFER_START bit clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * - clear XFER_STOP bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Stop a read transfer in fifo mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * - the hardware is to reset the XFER_START bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * after the number of bytes indicated in DIN_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * - just wait XFER_START bit clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (a3700_spi->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (a3700_spi->xmit_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * If there are data written to the SPI device, wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * until SPI_WFIFO_EMPTY is 1 to wait for all data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * transfer out of write FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!a3700_spi_transfer_wait(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) A3700_SPI_WFIFO_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&spi->dev, "wait wfifo empty timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(&spi->dev, "wait xfer ready timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val |= A3700_SPI_XFER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!(val & A3700_SPI_XFER_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(&spi->dev, "wait transfer start clear timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) val &= ~A3700_SPI_XFER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) a3700_spi_transfer_abort_fifo(a3700_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int a3700_spi_transfer_one_full_duplex(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Disable FIFO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) a3700_spi_fifo_mode_set(a3700_spi, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) while (a3700_spi->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* When we have less than 4 bytes to transfer, switch to 1 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * mode. This is reset after each transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (a3700_spi->buf_len < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) a3700_spi_bytelen_set(a3700_spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (a3700_spi->byte_len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val = *a3700_spi->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val = *(u32 *)a3700_spi->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Wait for all the data to be shifted in / out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) A3700_SPI_XFER_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) a3700_spi->buf_len -= a3700_spi->byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) a3700_spi->tx_buf += a3700_spi->byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) a3700_spi->rx_buf += a3700_spi->byte_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int a3700_spi_transfer_one(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct spi_transfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) a3700_spi_transfer_setup(spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (xfer->tx_buf && xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return a3700_spi_transfer_one_full_duplex(master, spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return a3700_spi_transfer_one_fifo(master, spi, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int a3700_spi_unprepare_message(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) clk_disable(a3700_spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct of_device_id a3700_spi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { .compatible = "marvell,armada-3700-spi", .data = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int a3700_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct device_node *of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct a3700_spi *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 num_cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) master = spi_alloc_master(dev, sizeof(*spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(dev, "master allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(dev, "could not find num-cs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) master->dev.of_node = of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) master->mode_bits = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) master->num_chipselect = num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) master->prepare_message = a3700_spi_prepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) master->transfer_one = a3700_spi_transfer_one;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) master->unprepare_message = a3700_spi_unprepare_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) master->set_cs = a3700_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SPI_RX_QUAD | SPI_TX_QUAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spi->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ERR(spi->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = PTR_ERR(spi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) spi->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) init_completion(&spi->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) spi->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (IS_ERR(spi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = clk_prepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_err(dev, "could not prepare clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk_get_rate(spi->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) A3700_SPI_MAX_PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) a3700_spi_init(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_name(dev), master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_err(dev, "could not request IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto error_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(dev, "Failed to register master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto error_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) error_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int a3700_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct spi_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct a3700_spi *spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk_unprepare(spi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct platform_driver a3700_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .of_match_table = of_match_ptr(a3700_spi_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .probe = a3700_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .remove = a3700_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) module_platform_driver(a3700_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_DESCRIPTION("Armada-3700 SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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