Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Based on spi-mt7621.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRIVER_NAME "spi-ar934x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AR934X_SPI_REG_FS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AR934X_SPI_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AR934X_SPI_REG_IOC		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AR934X_SPI_IOC_INITVAL		0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AR934X_SPI_REG_CTRL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AR934X_SPI_CLK_MASK		GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AR934X_SPI_DATAOUT		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AR934X_SPI_REG_SHIFT_CTRL	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AR934X_SPI_SHIFT_EN		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AR934X_SPI_SHIFT_CS(n)		BIT(28 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AR934X_SPI_SHIFT_TERM		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AR934X_SPI_SHIFT_VAL(cs, term, count)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	(term) << AR934X_SPI_SHIFT_TERM | (count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AR934X_SPI_DATAIN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct ar934x_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	else if (div > AR934X_SPI_CLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int ar934x_spi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if ((spi->max_speed_hz == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	    (spi->max_speed_hz > (sp->clk_freq / 2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		spi->max_speed_hz = sp->clk_freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		dev_err(&spi->dev, "spi clock is too low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int ar934x_spi_transfer_one_message(struct spi_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 					   struct spi_message *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct ar934x_spi *sp = spi_controller_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct spi_transfer *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct spi_device *spi = m->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long trx_done, trx_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 term = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int div, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	const u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	m->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	list_for_each_entry(t, &m->transfers, transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (t->speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			div = ar934x_spi_clk_div(sp, t->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			stat = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			goto msg_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		reg &= ~AR934X_SPI_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		reg |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		for (trx_done = 0; trx_done < t->len; trx_done += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			trx_cur = t->len - trx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			if (trx_cur > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				trx_cur = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			else if (list_is_last(&t->transfer_list, &m->transfers))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				term = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			if (t->tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				tx_buf = t->tx_buf + trx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				reg = tx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				for (i = 1; i < trx_cur; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 					reg = reg << 8 | tx_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 						   trx_cur * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			stat = readl_poll_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			if (stat < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				goto msg_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			if (t->rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				reg = ioread32(sp->base + AR934X_SPI_DATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				buf = t->rx_buf + trx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				for (i = 0; i < trx_cur; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 					buf[trx_cur - i - 1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					reg >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		m->actual_length += t->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) msg_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	m->status = stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id ar934x_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ .compatible = "qca,ar934x-spi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MODULE_DEVICE_TABLE(of, ar934x_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int ar934x_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct ar934x_spi *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!ctlr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_info(&pdev->dev, "failed to allocate spi controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* disable flash mapping and expose spi controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* restore pins to default state: CSn=1 DO=CLK=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ctlr->mode_bits = SPI_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ctlr->setup = ar934x_spi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ctlr->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ctlr->num_chipselect = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dev_set_drvdata(&pdev->dev, ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	sp = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	sp->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	sp->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	sp->clk_freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	sp->ctlr = ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ret = spi_register_controller(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ar934x_spi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct spi_controller *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct ar934x_spi *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ctlr = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	sp = spi_controller_get_devdata(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	spi_unregister_controller(ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	clk_disable_unprepare(sp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct platform_driver ar934x_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.of_match_table = ar934x_spi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.probe = ar934x_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.remove = ar934x_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) module_platform_driver(ar934x_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_ALIAS("platform:" DRIVER_NAME);