Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // AMD SPI controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2020, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Author: Sanjay R Mehta <sanju.mehta@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AMD_SPI_CTRL0_REG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AMD_SPI_EXEC_CMD	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AMD_SPI_FIFO_CLEAR	BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AMD_SPI_BUSY		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AMD_SPI_OPCODE_MASK	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AMD_SPI_ALT_CS_REG	0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AMD_SPI_ALT_CS_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AMD_SPI_FIFO_BASE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AMD_SPI_TX_COUNT_REG	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AMD_SPI_RX_COUNT_REG	0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AMD_SPI_STATUS_REG	0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AMD_SPI_MEM_SIZE	200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* M_CMD OP codes for SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AMD_SPI_XFER_TX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AMD_SPI_XFER_RX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct amd_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem *io_remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long io_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 rom_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline u8 amd_spi_readreg8(struct spi_master *master, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static inline void amd_spi_writereg8(struct spi_master *master, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				     u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 					 u8 set, u8 clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u8 tmp = amd_spi_readreg8(master, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	tmp = (tmp & ~clear) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	amd_spi_writereg8(master, idx, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline u32 amd_spi_readreg32(struct spi_master *master, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static inline void amd_spi_writereg32(struct spi_master *master, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				      u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					  u32 set, u32 clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 tmp = amd_spi_readreg32(master, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tmp = (tmp & ~clear) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	amd_spi_writereg32(master, idx, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void amd_spi_select_chip(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u8 chip_select = amd_spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			      AMD_SPI_ALT_CS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void amd_spi_clear_fifo_ptr(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			       AMD_SPI_FIFO_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			       AMD_SPI_OPCODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void amd_spi_set_rx_count(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					u8 rx_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void amd_spi_set_tx_count(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					u8 tx_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline int amd_spi_busy_wait(struct amd_spi *amd_spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	bool spi_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* poll for SPI bus to become idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		    AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	while (spi_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (timeout-- < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			    AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void amd_spi_execute_opcode(struct spi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* Set ExecuteOpCode bit in the CTRL0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			       AMD_SPI_EXEC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	amd_spi_busy_wait(amd_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int amd_spi_master_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct spi_master *master = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	amd_spi_clear_fifo_ptr(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				    struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				    struct spi_message *message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct spi_transfer *xfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u8 cmd_opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 *buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 m_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 tx_len = 0, rx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	list_for_each_entry(xfer, &message->transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			    transfer_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (xfer->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			m_cmd = AMD_SPI_XFER_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (xfer->tx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			m_cmd = AMD_SPI_XFER_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (m_cmd & AMD_SPI_XFER_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			buf = (u8 *)xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			tx_len = xfer->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			cmd_opcode = *(u8 *)xfer->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			amd_spi_set_opcode(master, cmd_opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			/* Write data into the FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			for (i = 0; i < tx_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				iowrite8(buf[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					 ((u8 __iomem *)amd_spi->io_remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 					 AMD_SPI_FIFO_BASE + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			amd_spi_set_tx_count(master, tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			amd_spi_clear_fifo_ptr(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			/* Execute command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			amd_spi_execute_opcode(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (m_cmd & AMD_SPI_XFER_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 * Store no. of bytes to be received from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			 * FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			rx_len = xfer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			buf = (u8 *)xfer->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			amd_spi_set_rx_count(master, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			amd_spi_clear_fifo_ptr(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			/* Execute command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			amd_spi_execute_opcode(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			/* Read data from FIFO to receive buffer  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			for (i = 0; i < rx_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				buf[i] = amd_spi_readreg8(master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 							  AMD_SPI_FIFO_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 							  tx_len + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Update statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	message->actual_length = tx_len + rx_len + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* complete the transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	message->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	spi_finalize_current_message(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int amd_spi_master_transfer(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				   struct spi_message *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct amd_spi *amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct spi_device *spi = msg->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	amd_spi->chip_select = spi->chip_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	amd_spi_select_chip(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * Extract spi_transfers from the spi message and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * program the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	amd_spi_fifo_xfer(amd_spi, master, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int amd_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct amd_spi *amd_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Allocate storage for spi_master and driver private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	master = spi_alloc_master(dev, sizeof(struct amd_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dev_err(dev, "Error allocating SPI master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	amd_spi = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	amd_spi->io_remap_addr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (IS_ERR(amd_spi->io_remap_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		err = PTR_ERR(amd_spi->io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		dev_err(dev, "error %d ioremap of SPI registers failed\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* Initialize the spi_master fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	master->bus_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	master->num_chipselect = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	master->mode_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	master->flags = SPI_MASTER_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	master->setup = amd_spi_master_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	master->transfer_one_message = amd_spi_master_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/* Register the controller with SPI framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	err = devm_spi_register_master(dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		dev_err(dev, "error %d registering SPI controller\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto err_free_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) err_free_master:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct acpi_device_id spi_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ "AMDI0061", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct platform_driver amd_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.name = "amd_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.acpi_match_table = ACPI_PTR(spi_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.probe = amd_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) module_platform_driver(amd_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("AMD SPI Master Controller Driver");