Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Altera SPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on spi_s3c24xx.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2006 Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spi/altera.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRV_NAME "spi_altera"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ALTERA_SPI_RXDATA	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ALTERA_SPI_TXDATA	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ALTERA_SPI_STATUS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ALTERA_SPI_CONTROL	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ALTERA_SPI_SLAVE_SEL	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ALTERA_SPI_STATUS_ROE_MSK	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ALTERA_SPI_STATUS_TOE_MSK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ALTERA_SPI_STATUS_TMT_MSK	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ALTERA_SPI_STATUS_TRDY_MSK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ALTERA_SPI_STATUS_RRDY_MSK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ALTERA_SPI_STATUS_E_MSK		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ALTERA_SPI_CONTROL_IROE_MSK	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ALTERA_SPI_CONTROL_ITOE_MSK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ALTERA_SPI_CONTROL_ITRDY_MSK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ALTERA_SPI_CONTROL_IRRDY_MSK	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ALTERA_SPI_CONTROL_IE_MSK	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ALTERA_SPI_CONTROL_SSO_MSK	0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ALTERA_SPI_MAX_CS		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) enum altera_spi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ALTERA_SPI_TYPE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ALTERA_SPI_TYPE_SUBDEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct altera_spi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	const unsigned char *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned char *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 regoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct regmap_config spi_altera_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int altr_spi_writel(struct altera_spi *hw, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			   unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ret = regmap_write(hw->regmap, hw->regoff + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		dev_err(hw->dev, "fail to write reg 0x%x val 0x%x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			reg, val, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int altr_spi_readl(struct altera_spi *hw, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			  unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ret = regmap_read(hw->regmap, hw->regoff + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_err(hw->dev, "fail to read reg 0x%x: %d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static inline struct altera_spi *altera_spi_to_hw(struct spi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return spi_master_get_devdata(sdev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct altera_spi *hw = altera_spi_to_hw(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (is_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				BIT(spi->chip_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void altera_spi_tx_word(struct altera_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int txd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (hw->tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		switch (hw->bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			txd = hw->tx[hw->count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			txd = (hw->tx[hw->count * 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				| (hw->tx[hw->count * 2 + 1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			txd = (hw->tx[hw->count * 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				| (hw->tx[hw->count * 4 + 1] << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				| (hw->tx[hw->count * 4 + 2] << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				| (hw->tx[hw->count * 4 + 3] << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	altr_spi_writel(hw, ALTERA_SPI_TXDATA, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void altera_spi_rx_word(struct altera_spi *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	altr_spi_readl(hw, ALTERA_SPI_RXDATA, &rxd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (hw->rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		switch (hw->bytes_per_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			hw->rx[hw->count] = rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			hw->rx[hw->count * 2] = rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			hw->rx[hw->count * 2 + 1] = rxd >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			hw->rx[hw->count * 4] = rxd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			hw->rx[hw->count * 4 + 1] = rxd >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			hw->rx[hw->count * 4 + 2] = rxd >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			hw->rx[hw->count * 4 + 3] = rxd >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	hw->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int altera_spi_txrx(struct spi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct spi_device *spi, struct spi_transfer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct altera_spi *hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	hw->tx = t->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	hw->rx = t->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	hw->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	hw->len = t->len / hw->bytes_per_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (hw->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/* enable receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		hw->imr |= ALTERA_SPI_CONTROL_IRRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		/* send the first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		altera_spi_tx_word(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	while (hw->count < hw->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		altera_spi_tx_word(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			if (val & ALTERA_SPI_STATUS_RRDY_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		altera_spi_rx_word(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static irqreturn_t altera_spi_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct spi_master *master = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct altera_spi *hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	altera_spi_rx_word(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (hw->count < hw->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		altera_spi_tx_word(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		/* disable receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		spi_finalize_current_transfer(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int altera_spi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	const struct platform_device_id *platid = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct altera_spi_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	enum altera_spi_type type = ALTERA_SPI_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct altera_spi *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct spi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	master = spi_alloc_master(&pdev->dev, sizeof(struct altera_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* setup the master state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	master->bus_num = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (pdata->num_chipselect > ALTERA_SPI_MAX_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				"Invalid number of chipselect: %hu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				pdata->num_chipselect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		master->num_chipselect = pdata->num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		master->mode_bits = pdata->mode_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		master->bits_per_word_mask = pdata->bits_per_word_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		master->num_chipselect = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		master->mode_bits = SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	master->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	master->transfer_one = altera_spi_txrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	master->set_cs = altera_spi_set_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	hw = spi_master_get_devdata(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	hw->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (platid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		type = platid->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* find and map our resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (type == ALTERA_SPI_TYPE_SUBDEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		struct resource *regoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		hw->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (!hw->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			dev_err(&pdev->dev, "get regmap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		regoff = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (regoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			hw->regoff = regoff->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		void __iomem *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		res = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		if (IS_ERR(res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			err = PTR_ERR(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		hw->regmap = devm_regmap_init_mmio(&pdev->dev, res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 						   &spi_altera_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (IS_ERR(hw->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			dev_err(&pdev->dev, "regmap mmio init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			err = PTR_ERR(hw->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* program defaults into the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	hw->imr = 0;		/* disable spi interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	altr_spi_writel(hw, ALTERA_SPI_STATUS, 0);	/* clear status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (val & ALTERA_SPI_STATUS_RRDY_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		altr_spi_readl(hw, ALTERA_SPI_RXDATA, &val); /* flush rxdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/* irq is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	hw->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (hw->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				       pdev->name, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	err = devm_spi_register_master(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		for (i = 0; i < pdata->num_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			if (!spi_new_device(master, pdata->devices + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					 "unable to create SPI device: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 					 pdata->devices[i].modalias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dev_info(&pdev->dev, "regoff %u, irq %d\n", hw->regoff, hw->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	spi_master_put(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct of_device_id altera_spi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ .compatible = "ALTR,spi-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	{ .compatible = "altr,spi-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DEVICE_TABLE(of, altera_spi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct platform_device_id altera_spi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{ DRV_NAME,		ALTERA_SPI_TYPE_UNKNOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	{ "subdev_spi_altera",	ALTERA_SPI_TYPE_SUBDEV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_DEVICE_TABLE(platform, altera_spi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct platform_driver altera_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.probe = altera_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.pm = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.of_match_table = of_match_ptr(altera_spi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.id_table	= altera_spi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) module_platform_driver(altera_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DESCRIPTION("Altera SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_ALIAS("platform:" DRV_NAME);