^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Atmel QSPI Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 Cryptera A/S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi-mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* QSPI register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QSPI_CR 0x0000 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QSPI_MR 0x0004 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QSPI_RD 0x0008 /* Receive Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QSPI_TD 0x000c /* Transmit Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QSPI_SR 0x0010 /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QSPI_IER 0x0014 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QSPI_IMR 0x001c /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QSPI_SCR 0x0020 /* Serial Clock Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QSPI_IAR 0x0030 /* Instruction Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QSPI_ICR 0x0034 /* Instruction Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QSPI_IFR 0x0038 /* Instruction Frame Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QSPI_RICR 0x003C /* Read Instruction Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QSPI_SKR 0x0044 /* Scrambling Key Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QSPI_VERSION 0x00FC /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Bitfields in QSPI_CR (Control Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QSPI_CR_QSPIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QSPI_CR_QSPIDIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QSPI_CR_SWRST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QSPI_CR_LASTXFER BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Bitfields in QSPI_MR (Mode Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QSPI_MR_SMM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QSPI_MR_LLB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QSPI_MR_WDRBT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QSPI_MR_SMRM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QSPI_SR_RDRF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QSPI_SR_TDRE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QSPI_SR_TXEMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QSPI_SR_OVRES BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QSPI_SR_CSR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QSPI_SR_CSS BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QSPI_SR_INSTRE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QSPI_SR_QSPIENS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Bitfields in QSPI_SCR (Serial Clock Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QSPI_SCR_CPOL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QSPI_SCR_CPHA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QSPI_ICR_INST_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Bitfields in QSPI_IFR (Instruction Frame Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QSPI_IFR_INSTEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QSPI_IFR_ADDREN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QSPI_IFR_OPTEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QSPI_IFR_DATAEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QSPI_IFR_OPTL_1BIT (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QSPI_IFR_OPTL_2BIT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QSPI_IFR_OPTL_4BIT (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QSPI_IFR_OPTL_8BIT (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QSPI_IFR_ADDRL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QSPI_IFR_TFRTYP_MEM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QSPI_IFR_CRM BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QSPI_SMR_SCREN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QSPI_SMR_RVDIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QSPI_WPMR_WPEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QSPI_WPSR_WPVS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct atmel_qspi_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool has_qspick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool has_ricr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct atmel_qspi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk *qspick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct atmel_qspi_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) resource_size_t mmap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct completion cmd_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct atmel_qspi_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 cmd_buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 addr_buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 data_buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct atmel_qspi_mode atmel_qspi_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case QSPI_CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return "CR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case QSPI_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return "MR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case QSPI_RD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return "MR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case QSPI_TD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return "TD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case QSPI_SR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return "SR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case QSPI_IER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return "IER";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case QSPI_IDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return "IDR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case QSPI_IMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return "IMR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case QSPI_SCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return "SCR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case QSPI_IAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return "IAR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case QSPI_ICR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return "ICR/WICR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case QSPI_IFR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return "IFR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case QSPI_RICR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return "RICR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case QSPI_SMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return "SMR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case QSPI_SKR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return "SKR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case QSPI_WPMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return "WPMR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case QSPI_WPSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return "WPSR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case QSPI_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return "VERSION";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) snprintf(tmp, sz, "0x%02x", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif /* VERBOSE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 value = readl_relaxed(aq->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) char tmp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif /* VERBOSE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) char tmp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif /* VERBOSE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel_relaxed(value, aq->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) const struct atmel_qspi_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (op->cmd.buswidth != mode->cmd_buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int atmel_qspi_find_mode(const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static bool atmel_qspi_supports_op(struct spi_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (atmel_qspi_find_mode(op) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* special case not supported by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) op->dummy.nbytes == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* DTR ops not supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (op->cmd.nbytes != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const struct spi_mem_op *op, u32 *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 iar, icr, ifr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 dummy_cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) iar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) icr = QSPI_ICR_INST(op->cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ifr = QSPI_IFR_INSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mode = atmel_qspi_find_mode(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ifr |= atmel_qspi_modes[mode].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (op->dummy.buswidth && op->dummy.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * The controller allows 24 and 32-bit addressing while NAND-flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * requires 16-bit long. Handling 8-bit long addresses is done using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * the option field. For the 16-bit addresses, the workaround depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * of the number of requested dummy bits. If there are 8 or more dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * cycles, the address is shifted and sent with the first dummy byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Otherwise opcode is disabled and the first byte of the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * contains the command opcode (works only if the opcode and address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * use the same buswidth). The limitation is when the 16-bit address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * used without enough dummy cycles and the opcode is using a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * buswidth than the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (op->addr.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) switch (op->addr.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (dummy_cycles < 8 / op->addr.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ifr &= ~QSPI_IFR_INSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ifr |= QSPI_IFR_ADDREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iar = (op->cmd.opcode << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (op->addr.val & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ifr |= QSPI_IFR_ADDREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iar = (op->addr.val << 8) & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dummy_cycles -= 8 / op->addr.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ifr |= QSPI_IFR_ADDREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) iar = op->addr.val & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) iar = op->addr.val & 0x7ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* offset of the data access in the QSPI memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *offset = iar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Set number of dummy cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (dummy_cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ifr |= QSPI_IFR_NBDUM(dummy_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Set data enable and data transfer type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ifr |= QSPI_IFR_DATAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (op->addr.nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ifr |= QSPI_IFR_TFRTYP_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * If the QSPI controller is set in regular SPI mode, set it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Serial Memory Mode (SMM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (aq->mr != QSPI_MR_SMM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) aq->mr = QSPI_MR_SMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (void)atmel_qspi_read(aq, QSPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (aq->caps->has_ricr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ifr |= QSPI_IFR_APBTFRTYP_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Set QSPI Instruction Frame registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) atmel_qspi_write(iar, aq, QSPI_IAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) atmel_qspi_write(icr, aq, QSPI_RICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) atmel_qspi_write(icr, aq, QSPI_WICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) atmel_qspi_write(ifr, aq, QSPI_IFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Set QSPI Instruction Frame registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) atmel_qspi_write(iar, aq, QSPI_IAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) atmel_qspi_write(icr, aq, QSPI_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) atmel_qspi_write(ifr, aq, QSPI_IFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 sr, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Check if the address exceeds the MMIO window size. An improvement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * would be to add support for regular SPI mode and fall back to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * when the flash memories overrun the controller's memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (op->addr.val + op->data.nbytes > aq->mmap_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) err = atmel_qspi_set_cfg(aq, op, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Skip to the final steps if there is no data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (op->data.nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) (void)atmel_qspi_read(aq, QSPI_IFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Send/Receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (op->data.dir == SPI_MEM_DATA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) memcpy_fromio(op->data.buf.in, aq->mem + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) memcpy_toio(aq->mem + offset, op->data.buf.out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) op->data.nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Release the chip-select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Poll INSTRuction End status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sr = atmel_qspi_read(aq, QSPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Wait for INSTRuction End interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reinit_completion(&aq->cmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) aq->pending = sr & QSPI_SR_CMD_COMPLETED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!wait_for_completion_timeout(&aq->cmd_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const char *atmel_qspi_get_name(struct spi_mem *spimem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return dev_name(spimem->spi->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .supports_op = atmel_qspi_supports_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .exec_op = atmel_qspi_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .get_name = atmel_qspi_get_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int atmel_qspi_setup(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct spi_controller *ctrl = spi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned long src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 scbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ctrl->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!spi->max_speed_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) src_rate = clk_get_rate(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!src_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Compute the QSPI baudrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (scbr > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) scbr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) aq->scr = QSPI_SCR_SCBR(scbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) atmel_qspi_write(aq->scr, aq, QSPI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void atmel_qspi_init(struct atmel_qspi *aq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Reset the QSPI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Set the QSPI controller by default in Serial Memory Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) aq->mr = QSPI_MR_SMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Enable the QSPI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct atmel_qspi *aq = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 status, mask, pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) status = atmel_qspi_read(aq, QSPI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mask = atmel_qspi_read(aq, QSPI_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pending = status & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) aq->pending |= pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) complete(&aq->cmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int atmel_qspi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct spi_controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct atmel_qspi *aq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int irq, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ctrl->setup = atmel_qspi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ctrl->bus_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ctrl->mem_ops = &atmel_qspi_mem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ctrl->num_chipselect = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ctrl->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) platform_set_drvdata(pdev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) aq = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) init_completion(&aq->cmd_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) aq->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Map the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) aq->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (IS_ERR(aq->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(&pdev->dev, "missing registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return PTR_ERR(aq->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Map the AHB memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) aq->mem = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (IS_ERR(aq->mem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(&pdev->dev, "missing AHB memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return PTR_ERR(aq->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) aq->mmap_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Get the peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) aq->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (IS_ERR(aq->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) aq->pclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (IS_ERR(aq->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(&pdev->dev, "missing peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return PTR_ERR(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Enable the peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err = clk_prepare_enable(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) aq->caps = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!aq->caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (aq->caps->has_qspick) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Get the QSPI system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) aq->qspick = devm_clk_get(&pdev->dev, "qspick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (IS_ERR(aq->qspick)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(&pdev->dev, "missing system clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) err = PTR_ERR(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Enable the QSPI system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = clk_prepare_enable(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "failed to enable the QSPI system clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Request the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto disable_qspick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0, dev_name(&pdev->dev), aq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto disable_qspick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) atmel_qspi_init(aq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) err = spi_register_controller(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto disable_qspick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) disable_qspick:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_disable_unprepare(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_disable_unprepare(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int atmel_qspi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct spi_controller *ctrl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spi_unregister_controller(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clk_disable_unprepare(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) clk_disable_unprepare(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int __maybe_unused atmel_qspi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct spi_controller *ctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) clk_disable_unprepare(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clk_disable_unprepare(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int __maybe_unused atmel_qspi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct spi_controller *ctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) clk_prepare_enable(aq->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) clk_prepare_enable(aq->qspick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) atmel_qspi_init(aq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) atmel_qspi_write(aq->scr, aq, QSPI_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) atmel_qspi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .has_qspick = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .has_ricr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct of_device_id atmel_qspi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .compatible = "atmel,sama5d2-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .data = &atmel_sama5d2_qspi_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .compatible = "microchip,sam9x60-qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .data = &atmel_sam9x60_qspi_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct platform_driver atmel_qspi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = "atmel_qspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .of_match_table = atmel_qspi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .pm = &atmel_qspi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .probe = atmel_qspi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .remove = atmel_qspi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) module_platform_driver(atmel_qspi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MODULE_DESCRIPTION("Atmel QSPI Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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